Method of forming CMOS imager with storage capacitor
View Patent ↗A CMOS imager having an improved signal to noise ratio and improved dynamic range is disclosed. The CMOS imager provides improved charge storage by fabricating a storage capacitor in parallel with the photocollection area of the imager. The storage capacitor may be a flat plate capacitor formed over the pixel, a stacked capacitor or a trench imager formed in the photosensor. The CMOS imager thus exhibits a better signal-to-noise ratio and improved dynamic range. Also disclosed are processes for forming the CMOS imager.
1. A method of forming a CMOS imager having improved charge storage comprising the steps of:
providing a semiconductor substrate having a doped layer of a first conductivity type;
forming a first doped region of a second conductivity type in said doped layer, wherein said first doped region is in contact with a charge collection region of a photosensor;
forming a storage capacitor over said substrate for storing charge accumulated by said charge collection region; and
forming a contact between said first doped region and said storage capacitor.
2. The method according to claim 1 , further comprising:
forming a second doped region of said second conductivity type in said doped layer spaced from said first doped region to transfer charge from said charge collection area;
forming a third doped region of said second conductivity type in said doped layer spaced from said second doped region wherein said third doped region effectuates the transfer of charge to a readout circuit; and
forming a fourth doped region of said second conductivity type in said doped layer spaced from said third doped region wherein said fourth doped region is a drain for a reset transistor for said CMOS imager.
3. The method according to claim 2 , wherein the first conductivity type is p-type, and the second conductivity type is n-type.
4. The method according to claim 2 , further comprising forming a photogate over said doped layer between said first and second doped regions.
5. The method according to claim 4 , further comprising forming a transfer gate over said doped layer between said second and said third doped regions.
6. The method according to claim 2 , wherein said first doped region, said second doped region, said third doped region and said fourth doped region are formed by ion implantation.
7. The method according to claim 6 , wherein said first doped region, said second doped region, said third doped region and said fourth doped region are doped with dopants selected from the group consisting of arsenic, antimony and phosphorous.
8. The method according to claim 7 , wherein the dopant is phosphorus.
9. The method according to claim 2 , further comprising forming an insulating layer over said semiconductor substrate.
10. The method according to claim 9 , wherein said storage capacitor is formed over said insulating layer and above said second doped region.
11. The method according to claim 9 , wherein said storage capacitor is a stacked storage capacitor formed in said insulating layer and said stacked storage capacitor is connected to said first doped region by said contact.
12. The method according to claim 11 , wherein said contact is formed of tungsten.
13. The method according to claim 11 , wherein said contact is formed of doped polysilicon.
14. The method according to claim 11 , wherein said stacked storage capacitor is formed by forming a trench in said insulating layer;
forming a first conductive layer in said trench;
forming an insulating layer over said first conductive layer; and
forming a second conductive layer over said insulating layer.
15. The method according to claim 14 , wherein said first conductive layer is formed by CVD or sputtering.
16. The method according to claim 14 , wherein said first conductive layer is a platinum metal layer, a tungsten metal layer, a titanium nitride layer or a doped polysilicon layer.
17. The method according to claim 14 , wherein said insulating layer is formed by CVD.
18. The method according to claim 14 , wherein said insulating layer is an oxide layer or a nitride layer.
19. The method according to claim 14 , wherein said second conductive layer is formed by CVD or sputtering.
20. The method according to claim 14 , wherein said second conductive layer is a platinum metal layer, a tungsten metal layer, a titanium nitride layer or a doped polysilicon layer.
21. The method according to claim 9 , wherein said storage capacitor is formed over said insulating layer and said storage capacitor is connected to said first doped region by said contact.
22. The method according to claim 21 , wherein said contact is formed of tungsten.
23. The method according to claim 21 , wherein said contact is formed of doped polysilicon.
24. The method according to claim 21 , wherein said storage capacitor is formed over a field oxide.
25. The method according to claim 21 , wherein said storage capacitor is formed by forming a first conductive layer over said insulating layer;
forming an insulating layer over said first conductive layer; and
forming a second conductive layer over said insulating layer.
26. The method according to claim 25 , wherein said first conductive layer is formed by CVD or sputtering.
27. The method according to claim 25 , wherein said first conductive layer is a platinum metal layer, a tungsten metal layer, a titanium nitride layer or a doped polysilicon layer.
28. The method according to claim 25 , wherein said insulating layer is formed by CVD.
29. The method according to claim 25 , wherein said insulating layer is an oxide layer or a nitride layer.
30. The method according to claim 25 , wherein said second conductive layer is a formed by CVD or sputtering.
31. The method according to claim 25 , wherein said second conductive layer is a platinum metal layer, a tungsten metal layer, a titanium nitride layer or a doped polysilicon layer.
32. The method according to claim 25 , further comprising etching the excess layers of said storage capacitor from said insulating layer.
33. A method of forming a CMOS imager having improved charge storage comprising the steps of:
providing a semiconductor substrate having a doped layer of a first conductivity type;
providing a photoconversion device in said semiconductor substrate for accumulating photogenerated charge, said photoconversion device comprising a light sensitive area;
forming a first doped region of a second conductivity type in said doped layer and adjacent said photoconversion device;
forming a trench in said doped layer adjacent to said first doped region;
forming a first conductive layer in said trench;
forming an insulating layer over said first conductive layer in said trench; and
forming a second conductive layer over said insulating layer to form a trench capacitor, wherein said trench capacitor is electrically connected in parallel with said light sensitive area and stores charge accumulated in said photoconversion device.
34. The method according to claim 33 , wherein said first conductive layer is formed by CVD or sputtering.
35. The method according to claim 34 , wherein said first conductive layer is a platinum metal layer, a tungsten metal layer, a titanium nitride layer or a doped polysilicon layer.
36. The method according to claim 33 , wherein said insulating layer is formed by CVD.
37. The method according to claim 36 , wherein said insulating layer is an oxide layer or a nitride layer.
38. The method according to claim 33 , wherein said second conductive layer is formed by CVD or sputtering.
39. The method according to claim 38 , wherein said second conductive layer is a platinum metal layer, a tungsten metal layer, a titanium nitride layer or a doped polysilicon layer.
40. The method according to claim 33 , wherein said trench forming step comprises a reactive ion etching process.
41. The method according to claim 40 , wherein said trench forming step comprises etching the substrate with a preferential anisotropic etchant.
42. The method according to claim 33 , further comprising:
forming a second doped region of said second conductivity type in said doped layer spaced from said first doped region;
forming a third doped region of said second conductivity type in said doped layer spaced from said second doped region; and
forming a fourth doped region of said second conductivity type in said doped layer spaced from said third doped region.
43. The method according to claim 42 , wherein the first conductivity type is p-type, and the second conductivity type is n-type.
44. The method according to claim 42 , further comprising forming an insulating layer over said semiconductor substrate.
45. The method according to claim 42 , further comprising forming a photogate over said doped layer between said first and second doped regions.
46. The method according to claim 45 , further comprising forming a transfer gate over said doped layer between said second and said third doped regions.
47. The method according to claim 42 , wherein said first doped region, said second doped region, said third doped region and said fourth doped region are formed by ion implantation.
48. The method according to claim 47 , wherein said first doped region, said second doped region, said third doped region and said fourth doped region are doped with dopants selected from the group consisting of arsenic, antimony and phosphorous.
49. The method according to claim 48 , wherein the dopant is phosphorus.
50. The method according to claim 49 , wherein said first doped region, said second doped region, said third doped region and said fourth doped region are doped at a dopant concentration of from about 1×10 15 ions/cm 2 to about 1×10 16 ions/cm 2 .