Semiconductor memory device
View Patent ↗A semiconductor memory device includes a memory cell array having a plurality of memory cells. The memory cells are arranged at intersections between a plurality of word lines and a plurality of bit lines. The semiconductor memory device also includes a row decoder section located adjacent to the memory cell array. The row decoder section has a plurality of decoder circuits which selectively drive the word lines. The semiconductor memory device further includes a control circuit section located adjacent to the row decoder section. The control circuit section has at least one control circuit whose part is arranged in the row decoder section.
1. A semiconductor memory device comprising:
a memory cell array including a plurality of memory cells which are arranged at intersections between a plurality of word lines and a plurality of bit lines;
a row decoder section located adjacent to said memory cell array, said row decoder section including n decoder circuits which selectively drive said word lines;
a control circuit section located adjacent to said row decoder section; and
at least one control circuit having a first part arranged in said control circuit section and a second part arranged in said row decoder section, said second part of said at least one control circuit being divided into n transistors which are distributively arranged in said n decoder circuits.
2. A semiconductor memory device according to claim 1 , wherein said n transistors are equal in size.
3. A semiconductor memory device according to claim 1 , wherein said n transistors have a signal amplitude level equal to that of said plurality of decoder circuits.
4. A semiconductor memory device comprising:
a memory cell array including a plurality of memory cells which are arranged at intersections between a plurality of word lines and a plurality of bit lines;
a row decoder section located adjacent to said memory cell array, said row decoder section including a plurality of decoder circuits which selectively drive said word lines;
a control circuit section located adjacent to said row decoder section; and
at least one control circuit having a first part arranged in said control circuit section and a second part arranged in said row decoder section, said second part of said at least one control circuit being divided into circuits which are distributively arranged in said plurality of decoder circuits,
wherein said at least one control circuit includes one of: a setting signal-generating circuit which sets said plurality of decoder circuits; a precharge signal-generating circuit which precharges said plurality of decoder circuits; and an equalize signal-generating circuit which causes a bit line equalizer circuit of a sense amplifier section to perform an equalize operation, and
said second part of at least one control circuit includes P-channel transistors of complementary metal oxide semiconductor type inverter circuits of said setting signal-generating circuit, precharge signal-generating circuit and equalize signal-generating circuit.
5. A semiconductor memory device according to claim 4 , wherein said inverter circuits use a predetermined internal power supply voltage as a power supply voltage.
6. A semiconductor memory device according to claim 4 , wherein said inverter circuits use a boosted voltage higher than an internal power supply voltage as a power supply voltage.
7. A semiconductor memory device comprising:
a memory cell array including a plurality of memory cells which are arranged at intersections between a plurality of word lines and a plurality of bit lines;
a row decoder section located adjacent to said memory cell array, said row decoder section including a plurality of decoder circuits which selectively drive said word lines;
a control circuit section located adjacent to said row decoder section; and
at least one control circuit having a first part arranged in said control circuit section and a second part arranged in said row decoder section, said second part of said at least one control circuit being divided into circuits which are distributively arranged in said plurality of decoder circuits.
wherein said at least one control circuit includes one of: a setting signal-generating circuit which sets said plurality of decoder circuits; a precharge signal-generating circuit which precharges said plurality of decoder circuits; and an equalize signal-generating circuit which causes a bit line equalizer circuit of a sense amplifier section to perform an equalize operation, and
said second part of at least one control circuit includes N-channel transistors of complementary metal oxide semiconductor type inverter circuits of said setting signal-generating circuit, precharge signal-generating circuit and equalize signal-generating circuit.
8. A semiconductor memory device according to claim 7 , wherein said inverter circuits use a predetermined internal power supply voltage as a power supply voltage.
9. A semiconductor memory device according to claim 7 , wherein said inverter circuits use a boosted voltage higher than an internal power supply voltage as a power supply voltage.
10. A semiconductor memory device according to claim 7 , wherein said N-channel transistors are voltage-relaxing transistors.
11. A semiconductor memory device according to claim 10 , wherein said N-channel transistors include gates to which a boosted voltage higher than an internal power supply voltage is applied.
12. A semiconductor memory device according to claim 10 , wherein said N-channel transistors include gates whose potential is fixed.
13. A semiconductor memory device comprising:
a memory cell array including a plurality of memory cells which are arranged at intersections between a plurality of word lines and a plurality of bit lines;
a row decoder section located adjacent to said memory cell array, said row decoder section including a plurality of decoder circuits which selectively drive said word lines;
a control circuit section located adjacent to said row decoder section; and
at least one control circuit having a first part arranged in said control circuit section and a second part arranged in said row decoder section, said second part of said at least one control circuit being divided into circuits which are distributively arranged in said plurality of decoder circuits,
wherein said at least one control circuit includes: a setting signal-generating circuit which sets said plurality of decoder circuits; a precharge signal-generating circuit which precharges said plurality of decoder circuits; and an equalize signal-generating circuit which causes a bit line equalizer circuit of a sense amplifier section to perform an equalize operation, and
said second part of at least one control circuit includes P-channel transistors of complementary metal oxide semiconductor type inverter circuits of said setting signal-generating circuit, precharge signal-generating circuit and equalize signal-generating circuit.
14. A semiconductor memory device according to claim 13 , wherein said inverter circuits use a predetermined internal power supply voltage as a power supply voltage.
15. A semiconductor memory device according to claim 13 , wherein said inverter circuits use a boosted voltage higher than an internal power supply voltage as a power supply voltage.
16. A semiconductor memory device comprising:
a memory cell array including a plurality of memory cells which are arranged at intersections between a plurality of word lines and a plurality of bit lines;
a row decoder section located adjacent to said memory cell array, said row decoder section including a plurality of decoder circuits which selectively drive said word lines;
a control circuit section located adjacent to said row decoder section; and
at least one control circuit having a first part arranged in said control circuit section and a second part arranged in said row decoder section, said second part of said at least one control circuit being divided into circuits which are distributively arranged in said plurality of decoder circuits,
wherein said at least one control circuit includes: a setting signal-generating circuit which sets said plurality of decoder circuits; a precharge signal-generating circuit which precharges said plurality of decoder circuits; and an equalize signal-generating circuit which causes a bit line equalizer circuit of a sense amplifier section to perform an equalize operation, and
said second part of at least one control circuit includes N-channel transistors of complementary metal oxide semiconductor type inverter circuits of said setting signal-generating circuit, precharge signal-generating circuit and equalize signal-generating circuit.
17. A semiconductor memory device according to claim 16 , wherein said inverter circuits use a predetermined internal power supply voltage as a power supply voltage.
18. A semiconductor memory device according to claim 16 , wherein said inverter circuits use a boosted voltage higher than an internal power supply voltage as a power supply voltage.
19. A semiconductor memory device according to claim 16 , wherein said N-channel transistors are voltage-relaxing transistors.
20. A semiconductor memory device according to claim 19 , wherein said N-channel transistors include gates to which a boosted voltage higher than an internal power supply voltage is applied.
21. A semiconductor memory device according to claim 19 , wherein said N-channel transistors include gates whose potential is fixed.