Microprocessor program addressing arrangement having multiple independent complete address generators

1. An address-generating arrangement for a microprocessor comprising:

a base address-generating unit including a plurality of base registers and at least one base arithmetic unit having an address output, said address output including a first address, wherein said first address is a complete address having width equal to the width of an address register useable in program execution;

an address-generating expansion unit having an address bus output, said address bus output including a second address that includes an address extension, wherein said second address is another complete address having width equal to the width of the address register useable in program execution; and

an interface for selectively connecting one of said address output and said address bus output to one of said plurality of base registers in said base address-generating unit,

wherein said base address-generating unit and said address-generating expansion unit are configured to substantially independently generate complete addresses namely said first and second addressees useable in microprocessor program execution, respectively.

2. The address-generating arrangement of claim 1 wherein said address-generating expansion unit comprises at least one expansion register and an expansion arithmetic unit.

3. The address-generating arrangement of claim 2 wherein said interface comprises one or more input data buses for supplying data from said base address-generating unit to said address-generating expansion unit and an output data bus for supplying data from said address-generating expansion unit to said base address-generating unit.

4. The address-generating arrangement of claim 3 wherein one of said input data buses supplies data from one of said base registers to said expansion arithmetic unit and said output data bus supplies data from said expansion arithmetic unit to one of said base registers.

5. The address-generating arrangement of claim 3 wherein said input data buses include an input data bus for supplying data from one of said base registers and an input data bus for supplying output data from said base arithmetic unit.

6. The address-generating arrangement of claim 3 further arranged to provide output data from one of said base arithmetic unit and said expansion arithmetic unit to a base register.

7. The address-generating arrangement of claim 3 wherein said input and output data buses are provided as internal buses in said base address-generating expansion unit.

8. The address-generating arrangement of claim 3 , further comprising a multiplexer, said output data bus supplying data from said expansion arithmetic unit to a base register via said multiplexer.

9. The address-generating arrangement of claim 1 wherein said interface is controlled by said microprocessor.