Apparatus and method for extending a microprocessor instruction set

1. An apparatus for extending a microprocessor instruction set, comprising:

translation logic, for translating an extended instruction into corresponding micro instructions, wherein said extended instruction comprises:

an extended prefix, for directing that an architectural extension be employed in the execution of an operation prescribed by said extended instruction; and

an extended instruction tag, for indicating said extended instruction prefix, wherein said extended instruction tag is an otherwise architecturally specified opcode within the microprocessor instruction set, and wherein said extended instruction tag comprises opcode F1 (ICE BKPT) in the x86 instruction set; and

extended execution logic, coupled to said translation logic, for receiving said corresponding micro instructions, and for employing said architectural extension in the execution of said operation.

2. The apparatus as recited in claim 1 , wherein said extended instruction further comprises architecturally specified data entities according to the microprocessor instruction set.

3. The apparatus as recited in claim 2 , wherein said architecturally specified data entities comprise:

an opcode entity, for prescribing said operation.

4. The apparatus as recited in claim 3 , wherein said extended prefix prescribes information required to employ said architectural extension in the execution of said operation.

5. The apparatus as recited in claim 2 , wherein said extended prefix comprises a plurality of bits, and wherein logic states of said plurality of bits prescribe a plurality of architectural extensions to the microprocessor instruction set.

6. The apparatus as recited in claim 1 , wherein said extended prefix comprises 8 bits.

7. The apparatus as recited in claim 1 , wherein said corresponding micro instructions comprise a micro opcode field and a micro opcode extension field.

8. The apparatus as recited in claim 7 , wherein said extended execution logic employs said micro opcode extension field to determine said architectural extension, and wherein said extended execution logic employs said micro opcode field to determine said operation.

9. The apparatus as recited in claim 1 , wherein said translation logic comprises:

escape instruction detection logic, for detecting said extended instruction tag; and

extended prefix decoding logic, coupled to said escape instruction detection logic,

for translating said extended prefix, and for configuring a micro opcode extension field within said corresponding micro instructions, said micro opcode extension field prescribing said architectural extension.

10. The apparatus as recited in claim 9 , wherein said translation logic further comprises: instruction decoding logic, for configuring other fields within said corresponding micro instructions, said other fields prescribing said operation according to the microprocessor instruction set.

11. In a microprocessor, an instruction extending mechanism, comprising:

an instruction extension, configured to direct the microprocessor to utilize an extended architecture feature during execution of a specified operation, wherein said instruction extension comprises one of the instructions in an instruction set architecture followed by an n-bit extended features prefix, said one of the instructions indicating said instruction extension and said n-bit extended features prefix indicating said extended architecture feature, wherein said one of the instructions comprises instruction ICE BKPT (i.e., opcode F1) in the x86 instruction set architecture; and

a translator, configured to receive said instruction extension, and configured to generate a sequence of micro instructions, said sequence directing extended execution logic to utilize said extended architecture feature during execution of said specified operation.

12. The instruction extending mechanism as recited in claim 11 , wherein said instruction extending mechanism further comprises:

a plurality of instruction parts, coupled to said instruction extension, configured to prescribe said specified operation.

13. The instruction extending mechanism as recited in claim 12 , wherein said plurality of instruction parts are formatted in accordance with said instruction set architecture.

14. The instruction extending mechanism as recited in claim 11 , wherein values of said n-bit extended features prefix are mapped to a plurality of extended architecture features that supplement said instruction set architecture.

15. The instruction extending mechanism as recited in claim 11 , wherein said n-bit extended features prefix comprises 8 bits.

16. The instruction extending mechanism as recited in claim 11 , wherein said sequence of micro instructions comprises a micro opcode field and a micro opcode extension field.

17. The instruction extending mechanism as recited in claim 16 , wherein said micro opcode field directs said extended execution logic to perform said specified operation and said micro opcode extension field directs said extended execution logic to utilize said extended architecture feature.

18. The instruction extending mechanism as recited in claim 11 , wherein said translator comprises:

an escape instruction detector, for detecting said one of the instructions; and

an extended prefix decoder, coupled to said escape instruction detector, for translating said n-bit extended features prefix, and for generating a micro opcode extension field within said sequence of micro instructions.

19. An instruction set extension apparatus, comprising:

an escape tag, for reception by a microprocessor translator, and for indicating that accompanying parts of a corresponding instruction prescribe an extended operation to be performed by a microprocessor, wherein said escape tag is an existing instruction within a microprocessor instruction set, and wherein said existing instruction comprises instruction ICE BKPT (i.e., opcode F1) in the x86 microprocessor instruction set; and

an extended features specifier, coupled to said escape tag and being one of said accompanying parts, for prescribing a supplemental portion of said extended operation, said supplemental portion being supplemental to that provided for by said microprocessor instruction set.

20. The instruction set extension apparatus as recited in claim 19 , wherein the remainder of said accompanying parts are configured according to said microprocessor instruction set to prescribe a basic portion of said extended operation, and wherein said basic portion and said supplemental portion together prescribe said extended operation.

21. The instruction set extension apparatus as recited in claim 20 , wherein the remainder of said accompanying parts comprise an opcode byte and optional address specifier bytes.

22. The instruction set extension apparatus as recited in claim 19 , wherein said extended features specifier comprises an 8-bit data entity.

23. The instruction set extension apparatus as recited in claim 19 , wherein said microprocessor translator translates said escape tag and said accompanying parts into corresponding micro instructions that direct extended execution logic to perform said extended operation.

24. The instruction set extension apparatus as recited in claim 19 , wherein said microprocessor translator comprises:

escape tag detection logic, for detecting said escape tag, and for directing that said accompanying parts be translated according to extended translation conventions; and

decoding logic, coupled to said escape tag detection logic, for performing translation of microprocessor instructions according to conventions of said microprocessor instruction set, and for performing translation of said accompanying parts according to said extended translation conventions to enable said extended operation.

25. A method for extending a microprocessor instruction set, comprising:

providing an extended instruction, the extended instruction including an extended tag along with an extended prefix, wherein the extended tag is one of the instructions in the microprocessor instruction set, and wherein said providing comprises using the one of the instructions from the x86 microprocessor instruction set as the extended tag, and said using comprises selecting the x86 ICE BKPT (i.e., opcode F1) instruction as the extended tag;

prescribing, via the extended prefix and remaining parts of the extended instruction, an extended operation to be performed, wherein the extended operation employs an architectural feature of a microprocessor that cannot be prescribed by the instructions in the microprocessor instruction set; and

employing the architectural feature in execution of the extended operation.

26. The method as recited in claim 25 , wherein said prescribing comprises:

first specifying a conventional portion of the extended operation, said first specifying employing another of the instructions in the microprocessor instruction set; and

second specifying a supplemental portion of the extended operation, said second specifying employing the extended prefix.

27. The method as recited in claim 25 , wherein said providing comprises employing an extended prefix that has a size of 8 bits.

28. The method as recited in claim 25 , wherein said employing comprises:

translating the extended instruction into micro instructions that direct the microprocessor to perform the extended operation; and

within extended execution logic, executing the micro instructions to perform the extended operation.

29. The method as recited in claim 28 , wherein said translating comprises:

within translation logic, detecting the extended tag; and

decoding the extended prefix and remaining parts of the extended instruction according to extended translation rules.