System and method for protecting a peripheral device against hot plug attacks
View Patent ↗A method is provided for preventing a peripheral device such as an ATA disc drive, which is restricted to use with a designated host, being hot-plugged to another system after the drive is unlocked. Thus, violation of privacy of data (eg. music/video) stored on the drive through a hot-plug attack may be avoided. This is accomplished by maintaining time synchronization between the drive and its designated host so that both devices obtain the same seed from time information to generate a validation number at any time that a read/write command is issued from the host.
1. A method of protecting a peripheral device designated to a host, the method comprising:
(a) maintaining time synchronization between the host and the peripheral device by passing timing information with a first command between the host and the peripheral device;
(b) utilizing the time synchronization to generate common data in the host and the peripheral device; and
(c) generating a respective validation code in the host based on a seed including the common data with each of a plurality of second commands and transferring the respective validation code with each of the plurality of second commands from the host to the peripheral device.
2. A method according to claim 1 including placing the respective validation code in a register associated with the host and transferring the respective validation code to the peripheral device with each of the plurality of second commands, which comprise read or write commands.
3. A method according to claim 2 wherein the register includes a Features register.
4. A method according to claim 1 wherein the validation code includes a random number.
5. A method according to claim 4 wherein the random number is generated by means of a formula in the form
X n+1 =P 1 ·X n+ P 2 mod N n= 0,1,2, . . .
wherein X 0 denotes the seed.
6. A method according to claim 1 wherein the time synchronization is maintained by periodically setting respective timers in the host and the peripheral device to an initial value based on the timing information.
7. A method according to claim 2 wherein the common data is transferred to the peripheral device in a manner which does not substantially affect read/write operations in the device.
8. A method according to claim 1 including generating a validation code in the peripheral device based on the common data and comparing the validation code generated in the peripheral device with the validation code generated in the host.
9. A method according to claim 8 wherein the peripheral device responds normally to commands from the host during the comparison.
10. A method according to claim 8 including generating a revised validation code when the comparison does not result in a match of the validation codes and comparing the revised validation code with the validation code generated in the host.
11. A method according to claim 8 including switching the peripheral device to a locked mode in which the peripheral device fails to respond to further commands from the host, when the comparison does not result in a match of the validation codes.
12. A system for protecting a peripheral device designated to a host, the system including:
(a) means for maintaining time synchronization between the host and the peripheral device by passing timing information with a first command between the host and the peripheral device;
(b) means utilizing the time synchronization for generating common data in the host and the peripheral device; and
(c) means for generating a respective validation code in the host based on a seed including the common data with each of a plurality of second commands and transferring the respective validation code with each of the plurality of second commands from the host to the peripheral device.
13. A system according to claim 12 including means for placing the respective validation code in a register associated with the host and means for transferring the respective validation code to the peripheral device with each of the plurality of second commands, which comprise read or write commands.
14. A system according to claim 13 wherein the register includes a Features register.
15. A system according to claim 12 wherein the validation code includes a random number.
16. A system according to claim 15 wherein the random number is generated by means of a formula in the form
X n+1 =P 1 ·X n +P 2 mod N n= 0,1,2, . . .
wherein X 0 denotes the seed.
17. A system according to claim 12 including respective timers in the host and the peripheral device and wherein the time synchronization is maintained by periodically setting the timers to an initial value based on the timing information.
18. A system according to claim 13 wherein the common data is transferred to the peripheral device in a manner which does not substantially affect read/write operations in the device.
19. A system according to claim 12 including means for generating a validation code in the peripheral device based on the common data and means for comparing the validation code generated in the peripheral device with the validation code generated in the host.
20. A system according to claim 19 wherein the peripheral device responds normally to commands from the host during the comparison.
21. A system according to claim 19 including means for generating a revised validation code when the comparison does not result in a match of the validation codes, and means for comparing the revised validation code with the validation code generated in the host.
22. A system according to claim 19 including switching the peripheral device to a locked mode in which the peripheral device fails to respond to further commands from the host, when the comparison does not result in a match of the validation codes.