IP Library Granted Patent US 6,933,786
Granted Patent B1
US 6,933,786 · App. 10/146,524 · Granted Aug 23, 2005

Amplifier circuit and method

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Quick Facts
Patent No.
US 6,933,786
App. No.
10/146,524
Granted
Aug 23, 2005
Kind
B1
Abstract

An amplifier system has a control circuit. An amplifier is coupled to the control circuit and has a controllable gain. A controllable input impedance circuit is coupled to the control circuit. When the gain of the amplifier is changed the controllable input impedance circuit's impedance is adjusted, so that the input impedance to the system remains essentially constant.

Claims (30)

1. An amplifier circuit comprising:

a trans-impedance amplifier having a discrete controllable gain settings; and

a controllable input impedance circuit coupled to the trans-impedance amplifier, set to have a constant input impedance.

2. The amplifier circuit of claim 1 , further including a control circuit coupled to the trans-impedance amplifier and the controllable input impedance.

3. The amplifier circuit of claim 2 , wherein the control circuit adjusts the controllable input impedance circuit to maintain a fixed input impedance when the controllable gain is adjusted.

4. The amplifier circuit of claim 1 , wherein the trans-impedance amplifier includes a gain control circuit coupled to an open loop amplifier.

5. The amplifier circuit of claim 4 , wherein the gain control circuit has a gain adjustment element.

6. The amplifier circuit of claim 5 , wherein the gain adjustment element includes a switch in parallel with a resistor.

7. The amplifier circuit of claim 5 , wherein the gain adjustment element is a controllable current source.

8. The amplifier circuit of claim 7 , wherein the open loop amplifier includes a differential amplifier.

9. A method of operating an amplifier circuit, comprising the steps of:

a) determining an output voltage;

b) determining a discrete feedback resistance setting based on the output voltage; and

c) determining an internal gain of the amplifier circuit based on the feedback resistance.

10. The method of claim 9 , wherein step (c) further includes the step of:

(c1) determining the feedback resistance to produce a constant input impedance.

11. The method of claim 9 , wherein step (b) further includes the step of:

(b1) altering an internal gain of the amplifier circuit.

12. An amplifier system comprising:

a control circuit;

an amplifier having a controllable gain coupled to the control circuit; and

a controllable input impedance circuit with discrete settings coupled to the control circuits set by the control circuit to have a constant input impedance.

13. The system of claim 12 , wherein the controllable input impedance circuit includes a variable feedback resistance.

14. The system of claim 13 , wherein the variable feedback resistance includes a first resistor in series with a first switch and a second resistor in series with a second switch.

15. The system of claim 14 wherein the first resistor is electrically in parallel with the second resistor.

16. The system of claim 12 , wherein the amplifier includes an open loop amplifier coupled to a gain adjustment element.

17. The system of claim 16 , wherein the gain adjustment element includes a switch in parallel with a resistor.

18. The system of claim 16 , wherein the gain adjustment element includes a controllable current source.

19. The system of claim 16 , wherein the open loop amplifier includes a differential amplifier.

20. The system of claim 19 , wherein the gain adjustment element has a pair of controllable current sources.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 16, 2025
From: MONTEREY RESEARCH LLC
To: SOUTHFORK IP HOLDINGS LLC
Reel/Frame 071299/0161 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2002
From: MOHANDAS, P.S.; ROHILLA, GAJENDER; SHAH, PULKIT
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 012914/0688 →