Granted Patent B2

US 6,996,658 · App. 10/152,656 · Granted Feb 7, 2006

Abstract

Claims (65)

1. A device accessible by a host processor for expanding access over a first bus to a second bus, said first bus and said second bus each being adapted to separately connect to respective ones of a plurality of bus-compatible devices, said device comprising: a link; a first circuit adapted to couple between said first bus and said link; and a second circuit adapted to couple between said link and said second bus, said first circuit and said second circuit each being independently operated as a PCI bridge and being operable to (a) send outgoing information serially through said link in a form different from that of said first bus and said second bus (b) approve an initial exchange between said first bus and said second bus in response to pending bus transactions having a characteristic signifying a destination across said device, and (c) allow said host processor, communicating through said first bus, to individually address different selectable ones of the bus-compatible devices on said second bus: (i) using on said first bus substantially the same type of addressing as is used to access devices on said first bus, and (ii) without first employing a second, intervening one of the bus-compatible devices on said second bus.

2. A device accessible by a host processor for expanding access over a first bus to a second bus, said first bus and said second bus each being adapted to separately connect to respective ones of a plurality of bus-compatible devices, said device comprising: a switch having a plurality of ports; a first circuit adapted to couple between said first bus and a first one of said ports of said switch; and a second circuit adapted to couple between a second one of said ports of said switch and said second bus, said first circuit and said second circuit each being independently operated as a PCI bridge and being operable to (a) send outgoing information serially through said switch in a form different from that of said first bus and said second bus (b) approve an initial exchange between said first bus and said second bus in response to pending bus transactions having a characteristic signifying a destination across said device, and (c) allow said host processor, communicating through said first bus, to individually address different selectable ones of the bus-compatible devices on said second bus: (i) using on said first bus substantially the same type of addressing as is used to access devices on said first bus, and (ii) without first employing a second, intervening one of the bus-compatible devices on said second bus.

3. A device accessible by a host processor for expanding access over a first bus to a remote device, wherein said device comprises: a link; and a first circuit adapted to couple between said first bus and said link; said first circuit being independently operated as a bridge, capable of supporting PCI Type 0 and Type 1 configuration cycles, and being operable to send outgoing information serially through said link in a form different from that of said first bus, and to allow said host processor, communicating through said first bus, to selectively address said remote device.

4. The device of claim 3 , further comprising said remote device, wherein said remote device is adapted to couple to said link, is responsive to PCI configuration cycles originating from said processor and further comprises a first storage element adapted to implement a standard PCI configuration space.

5. The device of claim 4 , wherein said host processor selectively addresses said remote device using substantially the same addressing scheme as is used on said first bus.

6. The device of claim 4 , wherein said first bus is PCI.

7. The device of claim 4 , whereby said host processor assigns said remote device a unique address range through the use of said configuration cycles, and wherein said first circuit further comprises a second storage element adapted to store information contained in said configuration cycles destined for said remote device.

8. The device of claim 7 , whereby said host processor addresses said remote device via memory addresses, wherein said unique address range comprises a range of memory addresses and said second storage element is adapted to store parameters identifying said unique address range.

9. The device of claim 7 , whereby said host processor addresses said remote device via I/O addresses, wherein said unique address range comprises a range of I/O addresses and said second storage element is adapted to store parameters identifying said unique address range.

10. The device of claim 7 , wherein said device comprises a plurality of links and wherein said first circuit is adapted to couple between said first bus and said plurality of links, and said second storage element stores the identity of the link through which said configuration cycles were transacted.

11. The device of claim 4 , wherein said device comprises a plurality of links and wherein said first circuit is adapted to couple between said first bus and said plurality of links.

12. The device of claim 3 , further comprising a second circuit adapted to couple between said link and a second bus, wherein said remote device is coupled to said second bus, and said second circuit is independently operable as a bridge, capable of supporting PCI Type 0 and Type 1 configuration cycles.

13. The device of claim 12 , wherein said host processor selectively addresses said remote device using on said second bus substantially the same addressing scheme as is used on said first bus.

14. The device of claim 12 , wherein said first bus is PCI.

15. The device of claim 12 , wherein said second bus is PCI.

16. The device of claim 12 , whereby said host processor assigns said remote device on said second bus a unique address range through the use of said configuration cycles, and wherein said first circuit further comprises a storage element adapted to store information contained in said configuration cycles destined for said remote device.

17. The device of claim 16 , whereby said host processor addresses said remote device via memory addresses, wherein said unique address range comprises a range of memory addresses and said storage element is adapted to store parameters identifying said unique address range.

18. The device of claim 16 , whereby said host processor addresses said remote device via I/O addresses, wherein said unique address range comprises a range of I/O addresses and said storage element is adapted to store parameters identifying said unique address range.

19. The device of claim 16 , wherein said device comprises a plurality of links and wherein said first circuit is adapted to couple between said first bus and said plurality of links, and said storage element stores the identity of the link through which said configuration cycles were transacted.

20. The device of claim 12 , wherein said device comprises a plurality of links and wherein said first circuit is adapted to couple between said first bus and said plurality of links.

21. The device of claim 3 , wherein said host processor selectively addresses said remote device using substantially the same addressing scheme as is used on said first bus.

22. The device of claim 3 , wherein said first bus is PCI.

23. The device of claim 3 , whereby said host processor assigns said remote device a unique address range through the use of said configuration cycles, and wherein said first circuit further comprises a second storage element adapted to store information contained in said configuration cycles destined for said remote device.

24. The device of claim 23 , whereby said host processor addresses said remote device via memory addresses, wherein said unique address range comprises a range of memory addresses and said second storage element is adapted to store parameters identifying said unique address range.

25. The device of claim 23 , whereby said host processor addresses said remote device via I/O addresses, wherein said unique address range comprises a range of I/O addresses and said second storage element is adapted to store parameters identifying said unique address range.

26. The device of claim 23 , wherein said device comprises a plurality of links and wherein said first circuit is adapted to couple between said first bus and said plurality of links, and said second storage element stores the identity of the link through which said configuration cycles were transacted.

27. The device of claim 3 , wherein said device comprises a plurality of links and wherein said first circuit is adapted to couple between said first bus and said plurality of links.

28. A device accessible by a host processor for expanding access over a first bus to a remote device, wherein said device comprises: a fabric comprising at least one switch, each of said at least one switch having a plurality of ports; and a first circuit adapted to couple between said first bus and a first port of said fabric; said first circuit being independently operated as a bridge, capable of supporting PCI Type 0 and Type 1 configuration cycles, and being operable to send outgoing information serially through said fabric in a form different from that of said first bus, and to allow said host processor, communicating through said first bus, to selectively address said remote device.

29. The device of claim 28 , further comprising said remote device, wherein said remote device is adapted to couple to a second port of said fabric, is responsive to PCI configuration cycles originating from said processor and further comprising a first storage element adapted to implement a standard PCI configuration space.

30. The device of claim 29 , wherein said host processor selectively addresses said remote device using substantially the same addressing scheme as is used on said first bus.

31. The device of claim 29 , wherein said fabric comprises one switch and said first and second ports are located on said one switch.

32. The device of claim 29 , wherein said fabric comprises a plurality of interconnected switches, and said first port is located on a different one of said plurality of switches than said second port.

33. The device of claim 29 , wherein said first bus is PCI.

34. The device of claim 29 , whereby said host processor assigns said remote device a unique address range through the use of said configuration cycles, wherein said first circuit further comprises a second storage element adapted to store information contained in said configuration cycles destined for said remote device.

35. The device of claim 34 , whereby said host processor addresses said remote device via memory addresses, wherein said unique address range comprises a range of memory addresses and said second storage element is adapted to store parameters identifying said unique address range.

36. The device of claim 34 , whereby said host processor addresses said remote device via I/O addresses, wherein said unique address range is a range of I/O addresses and said second storage element is adapted to store parameters identifying said unique address range.

37. The device of claim 34 , wherein said first circuit is adapted to couple to a plurality of switches within said fabric, and said second storage element stores the identity of the switch through which said configuration cycles were transacted.

38. The device of claim 29 , wherein said first circuit is adapted to couple to a plurality of switches within said fabric.

39. The device of claim 29 , wherein at least one of said at least one switch is operable as an independent bridge, capable of supporting PCI Type 0 and Type 1 configuration cycles.

40. The device of claim 28 , further comprising a second circuit adapted to couple between a second port of said fabric and a second bus, and wherein said remote device is coupled to said second bus, and said second circuit is independently operable as a bridge, capable of supporting PCI Type 0 and Type 1 configuration cycles.

41. The device of claim 40 , wherein said host processor selectively addresses said remote device on said second bus using on said second bus substantially the same addressing scheme as is used on said first bus.

42. The device of claim 40 , wherein said fabric comprises one switch and said first and second ports are located on said one switch.

43. The device of claim 40 , wherein said fabric comprises a plurality of interconnected switches, and said first port is located on a different one of said plurality of switches than said second port.

44. The device of claim 40 , wherein said first bus is PCI.

45. The device of claim 40 , wherein said second bus is PCI.

46. The device of claim 40 , whereby said host processor assigns said remote device on said second bus a unique address range through the use of said configuration cycles, wherein said first circuit further comprises a storage element adapted to store information contained in said configuration cycles destined for said remote device.

47. The device of claim 46 , whereby said host processor addresses said remote device via memory addresses, wherein said unique address range comprises a range of memory addresses and said storage element is adapted to store parameters identifying said unique address range.

48. The device of claim 46 , whereby said host processor addresses said remote device via I/O addresses, wherein said unique address range is a range of I/O addresses and said storage element is adapted to store parameters identifying said unique address range.

49. The device of claim 46 , wherein said first circuit is adapted to couple to a plurality of switches within said fabric, and said storage element stores the identity of the switch through which said configuration cycles were transacted.

50. The device of claim 40 , wherein said first circuit is adapted to couple to a plurality of switches within said fabric.

51. The device of claim 40 , wherein at least one of said at least one switch is operable as an independent bridge, capable of supporting PCI Type 0 and Type 1 configuration cycles.

52. The device of claim 28 , wherein said host processor selectively addresses said remote device using substantially the same addressing scheme as is used on said first bus.

53. The device of claim 28 , wherein said fabric comprises one switch and said first and second ports are located on said one switch.

54. The device of claim 28 , wherein said fabric comprises a plurality of interconnected switches, and said first port is located on a different one of said plurality of switches than said second port.

55. The device of claim 28 , wherein said first bus is PCI.

56. The device of claim 28 , whereby said host processor assigns said remote device a unique address range through the use of said configuration cycles, wherein said first circuit further comprises a second storage element adapted to store information contained in said configuration cycles destined for said remote device.

57. The device of claim 56 , whereby said host processor addresses said remote device via memory addresses, wherein said unique address range comprises a range of memory addresses and said second storage element is adapted to store parameters identifying said unique address range.

58. The device of claim 56 , whereby said host processor addresses said remote device via I/O addresses, wherein said unique address range is a range of I/O addresses and said second storage element is adapted to store parameters identifying said unique address range.

59. The device of claim 56 , wherein said first circuit is adapted to couple to a plurality of switches within said fabric, and said second storage element stores the identity of the switch through which said configuration cycles were transacted.

60. The device of claim 28 , wherein said first circuit is adapted to couple to a plurality of switches within said fabric.

61. The device of claim 28 , wherein at least one of said at least one switch is operable as an independent bridge, capable of supporting PCI Type 0 and Type 1 configuration cycles.

62. A switch adapted to couple between (1) a circuit, said circuit in communication with a host processor via a bus and being operated independently as a bridge, capable of supporting PCI Type 0 and Type 1 configuration cycles, and being operable to send outgoing information serially in a form different from that of said bus; and (2) a remote device, wherein said remote device is responsive to PCI configuration cycles originating from said processor and further comprises a storage element adapted to implement a standard PCI configuration space; said switch comprising a plurality of ports, and a storage element adapted to implement a standard PCI configuration space, whereby said switch is responsive to PCI configuration cycles originating from said processor.

63. The switch of claim 62 , wherein said switch is operable as an independent bridge, capable of supporting PCI Type 0 and Type 1 configuration cycles.

64. The device of claims 1 , 2 , 3 , 4 , 12 , 28 , 29 or 40 , wherein said first circuit is adapted to perform address translation.

65. The device of claim 64 , wherein said first circuit comprises a segment table.

Assignments (10)