Image processing apparatus implemented in IC chip
When a reverse reproduction is instructed, an MPEG video stream is once decoded and is converted to image video signals by a first display circuit. Thereafter, the image video signals are again recoded by an image input circuit and an MPEG video encoder, so as to be overwritten in a storage area of a hard disk. An MPEG video decoder reads out this recoded data sequence in a reverse time-series manner and decodes it successively. Then the thus decoded data are converted to image video signals by a second display circuit, so as to be displayed on a display.
1. An image processing apparatus, comprising integrally:
a first block including: a front-end decoder which decodes a first coded data sequence in a time series manner;
and a first display circuit which generates a first image video signal from data decoded by the front-end decoder;
a second block including: an image input circuit which converts the first image video signal, outputted from said first block, to a video data sequence; and an encoder which codes the video data sequence into a second coded data sequence;
a third block including: a back-end decoder which decodes the second coded data sequence outputted from said second block in a reverse time-series manner; and a second display circuit which generates a second image video signal from data decoded by the back-end decoder; and
a switching circuit which switches an output of the first image video signal from said first block functioning as forward reproduction and an output of the second image video signal from said third block functioning as reverse reproduction,
said first block, second block, third block and switching circuit being integrally mounted,
wherein the first image video signal from said first block are also inputted to said second and third blocks while being outputted as forward reproduction via said switching circuit, so as to form a stand-by state in preparation for a switching to reverse reproduction.
2. An image processing apparatus according to claim 1 , wherein said first block and third block are video reproducing LSIs, and said second block is a video recording LSI.
3. An image processing apparatus according to claim 1 , the first coded data sequence is coded in compliance with MPEG.