IP Library Granted Patent US 7,013,557
Granted Patent B2
US 7,013,557 · App. 10/157,012 · Granted Mar 21, 2006

Method of packaging electronic components without creating unnecessary solder balls

Assignee: NEC Corporation
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Quick Facts
Patent No.
US 7,013,557
App. No.
10/157,012
Granted
Mar 21, 2006
Kind
B2
Abstract

A method of packaging an electronic component having electrodes soldered on lands on a printed circuit board uses a mask pattern that corresponds to the lands onto which solder paste is deposited. Solder paste is printed on the lands using the mask which has a convex shape such that the edges of the solder paste lie inside the edges of the lands. The electrodes are then placed on the solder paste, and the solder paste is caused to reflow to solder the electrodes to the lands.

Claims (12)

1. A method of manufacturing a package including an electronic component, in which the electronic component has electrodes and is packaged on a printed circuit board in which lands having border edges have been formed in a pattern of arrangement that corresponds to said electrodes by soldering said electrodes to said lands; said method comprising steps of:

arranging a metal mask, in which openings are formed in a pattern corresponding to said lands, on said printed circuit board such that said openings are each positioned over respective said lands, said opening defined by edge regions surrounding said openings;

filling each of said openings with solder paste;

removing said metal mask;

placing said electronic component on said printed circuit board such that said electrodes are each placed on said solder paste; and

performing reflow of said solder paste to solder said electrodes to said lands;

wherein at least one of said openings of said metal mask is formed in a shape such that portions of said edge regions have straight edges and at least a part of said edge regions are positioned inside the border edges of said lands when said metal mask is arranged on said printed circuit board; and

wherein said edge regions of said at least one of said openings is in the shape of a five sided polygon forming a home plate-shape having a convex shape with a vertex facing toward said electronic component, said vertex positioned not inside the border edges of the lands; and

wherein said filling step fills said at least one opening with said solder paste comprises tin-zinc (Sn—Zn) solder that does not contain lead (Pb).

2. The method of manufacturing a package including an electronic component according to claim 1 , wherein said at least a part of said edge regions are positioned inside the border edges of said land in areas on said land in which said electrodes are placed.

3. The method of manufacturing a package including an electronic component according to claim 1 , wherein said electronic component is a leadless chip.

4. The method of manufacturing a package including an electronic component according to claim 1 , wherein said electronic component is a device having L-type leads.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2011
From: NEC CORPORATION
To: NEC PERSONAL COMPUTERS, LTD.
Reel/Frame 027154/0570 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2002
From: SAKAI, HIROSHI; SUZUKI, MOTOJI; IGARASHI, MAKOTO; TANAKA, AKIHIRO
To: NEC CORPORATION
Reel/Frame 013143/0125 →
Priority Claims (1)
JP 2001-166908 · Jun 1, 2001 · national
Continuity (1)
Related Publication 20020179322A1 · Dec 5, 2002