Calibrating a wire load model for an integrated circuit
View Patent ↗A method is taught for determining a calibrated wire load model. The calibrated wire load model can be used to reach timing closure for an integrated circuit. The method includes; determining a reference timing description; determining a wire load model based on synthesis; determining a wire load model based connectivity; comparing the wire load model based on connectivity to the reference timing description. The method teaches adjusting the wire load model based on connectivity to determine a wire load model which faciliates timing closure. The method also teaches comparing the wire load model (based on synthesis) with the reference timing description. The disclosure contemplates a computer program product based upon the method taught. The disclosure further contemplates an integrated circuit designed based on the method taught. In another embodiment a computer system or another electronic system includes an integrated circuit designed by the method taught.
1. A method of creating a wire load model for an integrated circuit, the method comprising:
synthesizing a first netlist of components for the integrated circuit;
generating a non-timing driven placement of the first netlist of components;
generating a timing driven placement of the first netlist of components;
identifying one of several wire load models;
calculating first timing data based on the identified wire load model and the non-timing placement of the first netlist components;
generating a first histogram from the first timing data;
generating a parasitic estimation model from the timing driven placement of the first netlist of components;
calculating second timing data based on the parasitic estimation model;
generating a second histogram from the second timing data;
synthesizing a second netlist of components for the integrated circuit;
calculating a wire load model for the second netlist of components;
calculating third timing data based on the wire load model for the second netlist of components;
generating a third histogram from the third timing data
comparing the first and second histograms;
comparing the second and third histograms; and
creating a calibrated wire load model in response to comparing the first and second histograms and in response to comparing the second and third histograms.
2. A computer readable medium that stores instructions executable by a computer system, wherein the computer system implements a method for creating a wire load model for an integrated circuit in response to executing the instructions, the method comprising;
synthesizing a first netlist of components for the integrated circuit;
generating a non-timing driven placement of the first netlist of components;
generating a timing driven placement of the first netlist of components;
calculating first timing data based on the non-timing placement of the first netlist components;
generating a first histogram from the first timing data;
calculating second timing data based on the timing driven placement of the first netlist of components;
generating a second histogram from the second timing data;
synthesizing a second netlist of components for the integrated circuit;
calculating third timing data based on the second netlist of components;
generating a third histogram from the third timing data;
comparing the first and second histograms;
comparing the second and third histograms; and
creating a calibrated wire load model in response to comparing the first and second histograms and in response to comparing the second and third histograms.
3. The computer readable medium of claim 2 wherein the method further comprises:
identifying one of several wire load models;
wherein the first timing data is calculated based on the identified wire load model and the non-timing placement of the first netlist components.
4. The computer readable medium of claim 2 wherein the method further comprises:
generating a parasitic estimation model from the timing driven placement of the first netlist of components;
wherein the second histogram is generated based on the parasistic estimation model.
5. The computer readable medium of claim 2 wherein the method further comprises:
calculating a wire load model for the second netlist of components;
wherein the third timing data is calculated based on the wire load model for the second netlist of components.
6. A computer system comprising:
a processor,
a memory coupled to the processor; and
a set of instructions stored in the memory, wherein the set of instructions are executable by the processor, wherein the computer system implements a method for creating a wire load model for an integrated circuit in response to the processor executing the set of instructions, the method comprising:
synthesizing a first netlist of components for the integrated circuit;
generating a non-timing driven placement of the first netlist of components;
generating a timing driven placement of the first netlist of components;
calculating first timing data based on the non-timing placement of the first netlist components;
generating a first histogram from the first timing data;
calculating second timing data based on the timing driven placement of the first netlist of components;
generating a second histogram from the second timing data;
synthesizing a second netlist of components for the integrated circuit;
calculating third timing data based on the second netlist of components;
generating a third histogram from the third timing data;
comparing the first and second histograms;
comparing the second and third histograms; and
creating a calibrated wire load model in response to comparing the first and second histograms and in response to comparing the second and third histograms.
7. The computer system of claim 6 wherein the method further comprises:
identifying one of several wire load models;
wherein the first timing data is calculated based on the identified wire load model and the non-timing placement of the first netlist components.
8. The computer system of claim 6 wherein the method further comprises:
generating a parasitic estimation model from the timing driven placement of the first netlist of components;
wherein the second histogram is generated based on the parasistic estimation model.
9. The computer system of claim 6 wherein the method further comprises:
calculating a wire load model for the second netlist of components;
wherein the third timing data is calculated based on the wire load model for the second netlist of components.