Method and apparatus for reducing the power consumed by a computer system
A computer system having one or more components capable of being in either wake or sleep states includes a power manager and a voltage regulator. The power manager may generate a power state signal indicating the power state of the component, and this signal may be provided to the voltage regulator. The voltage regulator may supply power to the component. The target voltage level of the power may be dependent on both a current level of the power and the power state signal.
1. A voltage regulator comprising:
an output port to supply power to a component of a computer system, a target voltage level of the power to increase if a current level of the power decreases;
an input port to receive a power state signal, the target voltage level to decrease when the component transitions to a sleep state as indicated by the power state signal; and
a feedback line to couple the output port to the input port, a feedback voltage of the feedback line to be adjusted according to the power state signal, wherein the input port is coupled to a gate of a transistor, the transistor having a source/drain region coupled to the feedback line via a resistor to reduce the feedback voltage of the feedback line when the transistor is turned on.
2. The voltage regulator of claim 1 , wherein the target voltage level is to decrease if the current level increases.
3. The voltage regulator of claim 1 , wherein the target voltage level is to be inversely proportional to the current level while the component is in a wake state as indicated by the power state signal.
4. The voltage regulator of claim 1 , wherein the target voltage level is to increase when the component transitions to a wake state as indicated by the power state signal.
5. The voltage regulator of claim 1 , wherein the target voltage level is to decrease to within 25 mV of a lower specified supply voltage limit of the component when the component transitions to a sleep state as indicated by the power state signal.
6. The voltage regulator of claim 1 , further comprising a feedback line to couple the output port to the input port, a feedback voltage of the feedback line to be adjusted according to the power state signal.
7. The voltage regulator of claim 1 , wherein the power state signal is to indicate a power state of a plurality of components.
8. The voltage regulator of claim 1 , wherein the component is a processor.
9. A voltage regulator comprising:
an output port to supply power to a component of a computer system, a target voltage level of the power to increase if a current level of the power decreases;
an input port to receive a power state signal, the target voltage level to decrease when the component transitions to a sleep state as indicated by the power state signal; and
a feedback line to couple the output port to the input port, a feedback voltage of the feedback line to be adjusted according to the power state signal, wherein the input port is coupled to a diode, the diode coupled to the feedback line via a resistor to reduce the feedback voltage of the feedback line when the diode is forward biased.
10. The voltage regulator of claim 9 , wherein the diode is forward biased when the power state signal is low.
11. A computer system comprising:
a component to transition from a sleep state to a wake state;
a voltage regulator to supply power to the component, a target voltage level of the power to increase when the component transitions from the sleep state to the wake state, the target voltage level to be related to a current level of the power while the component is in a wake state, the voltage regulator including
an output port to supply power to the component,
an input port to receive a power state signal, the target voltage level to decrease when the component transitions to a sleep state as indicated by the power state signal, and
a feedback line to couple the output port to the input port a feedback voltage of the feedback line to be adjusted according to the power state signal, wherein the input port is coupled to a gate of a transistor, the transistor having a source/drain region coupled to the feedback line via a resistor to reduce the feedback voltage of the feedback line when the transistor is turned on.
12. The computer system of claim 11 , wherein the component is a processor.
13. The computer system of claim 12 , further comprising a power manager to indicate a power state of the component to the voltage regulator.
14. The computer system of claim 13 , wherein the power manager is to indicate the transition from the sleep state to the wake state to the voltage regulator before the component transitions from the sleep state to the wake state, the target voltage level to increase before the component transitions from the sleep state to the wake state.
15. The computer system of claim 13 , wherein the power manager is to indicate a transition of the component from the wake state to the sleep state to the voltage regulator before the component transitions from the wake state to the sleep state, the target voltage level to decrease before the component transitions from the wake state to the sleep state.
16. The computer system of claim 13 , further comprising a chipset including the power manager.
17. The computer system of claim 11 , wherein the target voltage level is to decrease if the current level increases, and the target voltage level is to increase if the current level decreases while the component is in the wake state.
18. The computer system of claim 11 , wherein the target voltage level is to be inversely proportional to the current level.
19. The computer system of claim 11 , wherein the target voltage level is to decrease when the component transitions from the wake state to the sleep state.
20. The computer system of claim 19 , wherein the target voltage level is to decrease to within 2.5% of a lower specified supply voltage limit of the component when the component transitions to the sleep state.
21. The computer system of claim 11 , wherein the voltage regulator is to supply the power to a plurality of components.
22. The computer system of claim 11 , wherein the voltage regulator is a switching voltage regulator.
23. A method comprising:
coupling a component to a power manager, the component to operate in sleep and wake states;
coupling the power manger to a voltage regulator to provide a power state signal to the voltage regulator to indicate a power state of the component; and
coupling the voltage regulator to the component to supply power to the component, a target voltage level of the power to be inversely proportional to a current level of the power when the component is operating in the wake state, the target voltage level to increase when the component transitions from the sleep to the wake state, as indicated by the power state signal, the voltage regulator including
an output port to supply power to the component,
an input port to receive a power state signal, the target voltage level to decrease when the component transitions to a sleep state as indicated by the power state signal, and
a feedback line to couple the output port to the input port, a feedback voltage of the feedback line to be adjusted according to the power state signal, wherein the input port is coupled to a gate of a transistor, the transistor having a source/drain region coupled to the feedback line via a resistor to reduce the feedback voltage of the feedback line when the transistor is turned on.
24. The method of claim 23 , wherein coupling the component to the power manager includes coupling a processor to a chipset.
25. The method of claim 23 , wherein the target voltage level is to decrease when the component transitions from the wake state to the sleep state, as indicated by the power state signal.
26. The method of claim 25 , wherein the target voltage level is to decrease to within 5% of a lower specified supply voltage limit of the component when the component transitions to the sleep state.
27. The method of claim 23 , further comprising coupling a plurality of components to the power manager, each of the plurality of components to operate in sleep and wake states, the power state signal to indicate the power state of the plurality of components.
28. The method of claim 23 , wherein coupling the voltage regulator to the component includes coupling a switching voltage regulator to the component.
29. A computer system comprising:
a component;
a power manager to provide a power state signal to indicate a power state of the component; and
a voltage regulator to supply power to the component, a target voltage level of the power to be dependent on both a current level of the power and the power state signal, the target voltage level increasing when the power state signal indicates a transition from a sleep state to a wake state, and the target voltage level decreasing when the power state signal indicates a transition from the wake state to the sleep state, the voltage regulator including
an output port to supply power to the component,
an input port to receive the power state signal, and
a feedback line to couple the output port to the input port, a feedback voltage of the feedback line to be adjusted according to the power state signal, wherein the input port is coupled to a diode, the diode coupled to the feedback line via a resistor to reduce the feedback voltage of the feedback line when the diode is forward biased.
30. The computer system of claim 29 , wherein the component is a processor.
31. The computer system of claim 29 , further comprising a chipset including the power manager.
32. The computer system of claim 29 , wherein the target voltage level is to be inversely proportional to the current level.