Patent Assignment
Reel/Frame 032893/0199
Assignment of Assignor's Interest
Recorded: 2014-05-14
Pages: 16
Assignor
INTEL CORPORATION
Executed: 2014-04-02
Assignee
SONY CORPORATION OF AMERICA
550 MADISON AVENUE, NEW YORK, NEW YORK, 10022-3211
Covered Properties
(129)
Method and Apparatus for Transferring Information Between a Processor and a Memory System
Patent:
5,701,503 →
Application:
08/360,331 →
Method and Apparatus for Maintaining Cache Coherency Using a Single Controller for Multiple Cache Memories
Patent:
5,832,534 →
Application:
08/550,777 →
Adjusting Clock Frequency and Voltage Supplied to a Processor in a Computer System
Patent:
5,760,636 →
Application:
08/673,452 →
Method and Apparatus for Maintaining Cache Coherency Using a Single Controller for Multiple Cache Memories
Patent:
5,903,908 →
Application:
08/731,546 →
Memory Subsystem Wherein a Single Processor Chip Controls Multiple Cache Memory Chips
Patent:
5,678,020 →
Application:
08/757,959 →
Method and Apparatus for Cache Memory Replacement Line Indentification
Patent:
5,809,524 →
Application:
08/822,044 →
Processor-Cache Protocol Using Simple Commands to Implement a Range of Cache Configurations
Patent:
6,202,125 →
Application:
08/851,845 →
Method and Apparatus for Controlling Multiple Dice with a Single Die
Patent:
5,966,722 →
Application:
08/891,303 →
Software-Controlled Cache Memory Compartmentalization
Method and Apparatus for Limiting Processor Clock Frequency
Patent:
6,385,735 →
Application:
08/990,526 →
Read Line Buffer and Signaling Protocol for Processor
Patent:
6,209,068 →
Application:
08/999,242 →
Method and Apparatus for Self-Calibration and Fixed-Pattern Noise Removal in Imager Integrated Circuits
Patent:
6,433,822 →
Application:
09/052,749 →
Method and Apparatus for Reducing Standby Leakage Current Using a Transistor Stack Effect
Patent:
6,169,419 →
Application:
09/151,177 →
Method and Apparatus for Reducing Standby Leakage Current Using a Leakage Control Transistor That Receives Boosted Gate Drive During an Active Mode
Managing a System's Performance State
Speculative Request Pointer Advance for Fast Back-to-Back Reads
Patent:
6,385,703 →
Application:
09/205,647 →
Snoop Blocking for Cache Coherency
Patent:
6,460,119 →
Application:
09/210,641 →
Method and Device for Filtering Events in an Event Notification Service
Patent:
6,438,618 →
Application:
09/212,023 →
Method and System for Bypassing a Fill Buffer Located Along a First Instruction Path
Patent:
6,442,674 →
Application:
09/223,297 →
Software Control of Transistor Body Bias in Controlling Chip Parameters
Programmable Thermal Management of an Integrated Circuit Die
Patent:
6,393,374 →
Application:
09/281,237 →
Circuit for I/O Clock Generation
Patent:
6,477,657 →
Application:
09/302,168 →
Integrated Circuit Low Leakage Power Circuitry for Use with an Advanced Cmos Process
Patent:
6,166,985 →
Application:
09/302,729 →
Processor System with Power Supply Selection Mechanism
Patent:
6,453,421 →
Application:
09/316,683 →
System and Method for Dynamically Adjusting to Cpu Performance Changes
Patent:
6,823,516 →
Application:
09/371,751 →
Sleep State Transitioning
Patent:
6,571,333 →
Application:
09/434,973 →
Error Character Generation
Patent:
6,438,728 →
Application:
09/461,395 →
Method and Apparatus That Compensates for Phase Shift Mask Manufacturing Defects
Patent:
6,428,936 →
Application:
09/465,520 →
Radio-Frequency Mixer for Wireless Applications
Patent:
6,466,775 →
Application:
09/467,342 →
Cache States for Multiprocessor Cache Coherency Protocols
Patent:
6,519,685 →
Application:
09/470,274 →
Arbitrating Command Requests in a Parallel Multi-Threaded Processing System
Patent:
6,532,509 →
Application:
09/470,541 →
Addressing of Monolithic Texture Maps
Patent:
6,429,873 →
Application:
09/474,182 →
Method and Apparatus to Control Processor Power and Performance for Single Phase Lock Loop (Pll) Processor Systems
Patent:
6,442,697 →
Application:
09/534,187 →
Method and Apparatus for Mobile Device Location via a Network Based Local Area Augmentation System
Patent:
7,126,527 →
Application:
09/603,451 →
Snoop Filter Line Replacement for Reduction of Back Invalidates in Multi-Node Architectures
Patent:
6,598,123 →
Application:
09/606,848 →
Method and Apparatus for Integrated Circuit Power Up
Patent:
6,448,824 →
Application:
09/676,728 →
Method and Apparatus for Fully-Differential Half-Circulator for Bi-Directional Small-Signal Signaling
Patent:
6,445,220 →
Application:
09/717,465 →
Low-Power Processor Hint, Such as from a Pause Instruction
Method of Copper Electroplating
External Attached Heat Sink Fold Out
Wafer Polishing Pad Centering Apparatus
Dynamically Changing the Performance of Devices in a Computer Platform
Computer Peripheral Device That Remains Operable When Central Processor Operations Are Suspended
Methods and Apparatus for Thermal Management of an Integrated Circuit Die
Double Data Rate Dynamic Logic
Patent:
6,441,648 →
Application:
09/852,442 →
Thermal Management System for a Multiple Processor Computer Appliance
Patent:
6,462,948 →
Application:
09/887,069 →
Uploading Personal Agents to Personalize Network Services
Method and Apparatus for Adjusting the Voltage and Frequency to Minimize Power Dissipation in a Multiprocessor System
Method and Apparatus for Enabling a Low Power Mode for a Processor
Active Leakage Control in Single-Ended Full-Swing Caches
Digital Throttle for Multiple Operating Points
Pseudo Least-Recently-Used (Plru) Replacement Method for a Multi-Node Snoop Filter
Method and Apparatus for Limiting Processor Clock Frequency
Set Partitioning for Caches Memories
Adaptive Receiver for Multiplex/Multi-Access Communications
Method and Apparatus for Testing a Circuit Using a Die Frame Logic Analyzer
A Method and an Apparatus for Reduction of Qos Impairments in Multi-Media Services During Hand-Over
Altering Operating Frequency and Voltage Set Point of a Circuit in Response to the Operating Temperature and Instantaneous Operating Voltage of the Circuit
System and Method for Loading and Integrating a Firmware Extension Onto Executable Base System Firmware During Initialization
Method and Apparatus for Reducing the Power Consumed by a Computer System
Method for Eliminating Redundant Method Calls in an Object Oriented Program
Identifying Pure Pointers to Disambiguate Memory References
Method and Apparatus to Control Processor Power and Performance for Single Phase Lock Loop (Pll) Processor Systems
Detecting Deadlocks in Multithreaded Programs
Snoop Blocking for Cache Coherency
Method and Apparatus for Shared Cache Coherency for a Chip Multiprocessor or Multiprocessor System
Apparatus for Thermal Management of Multiple Core Microprocessors
Method and Apparatus for Performance Effective Power Throttling
Method and Apparatus to Dynamically Change an Operating Frequency and Operating Voltage of an Electronic Device
Controlling the Timing of Test Modes in a Multiple Processor System
Method for Managing Virtual and Actual Performance States of Logical Processors in a Multithreaded Processor Using System Management Mode
Active State Link Power Management
Parallel Multi-Threaded Processing
Snoop Blocking for Cache Coherency
Cache States for Multiprocessor Cache Coherency Protocols
Method of Initializing a Memory Controller by Executing Software in a Second Memory to Wake Up a System
Snoop Filter Line Replacement for Reduction of Back Invalidates in Multi-Node Architectures
Filter Based Throttling
Method for Read Once Memory
Power Management for Clustered Computing Platforms
A Method to Remove Stale Branch Predictions for an Instruction Prior to Execution Within a Microprocessor
Method and Apparatus for Limiting Processor Clock Frequency
Methods and Apparatus to Enable Console Redirection in a Multiple Execution Environment
Method and System for Allocating Register Locations in a Memory During Compilation
Method, System, and Apparatus for Dynamically Configuring the Operating Point Utilized for Thermal Management of an Integrated Circuit
Wafer Reuse Techniques
Method and Apparatus to Clamp Sram Supply Voltage
Offset Cancellation and Slice Adjust Amplifier Circuit
Low-Power Processor Hint, Such as from a Pause Instruction
Methods and Apparatus for Thermal Management of an Integrated Circuit Die
Methods and Apparatus for Thermal Management of an Integrated Circuit Die
Method and Apparatus to Dynamically Change an Operating Frequency and Operating Voltage of an Electronic Device
Systems and Methods for Provisioning and Tracking a Communication Platform with a Radio-Frequency Tag
Pushing of Clean Data to One or More Processors in a System Having a Coherency Protocol
Coordinating Idle State Transitions in Multi-Core Processors
Operation and Control of Wireless Appliance Networks
Method and Apparatus for Improved Performance for Priority Agent Requests When Symmetric Agent Bus Parking Is Enabled
Method, Apparatus, and System for Memory Read Transaction Biasing in Mirrored Mode to Provide Thermal Management
Apparatus for Thermal Management of Multiple Core Microprocessors
Compressing Microcode
Patent:
7,095,342 →
Application:
11/096,152 →
Parallel Multi-Threaded Processing
Patent:
41,849 →
Application:
11/159,427 →
Method and System for Link Jitter Compensation Including a Fast Data Recovery Circuit
Arrangements for Initialization-Time and Run-Time Integration of Firmware and Software Extensions for Supporting Add-in Hardware
Transaction Detection in Link Based Computing System
Dual Bit Encoding / Decoding of Rfid Signal
Method and Apparatus for Enabling a Low Power Mode for a Processor
Method and Apparatus to Clamp Sram Supply Voltage
Convertible Display
Power Switches Having Positive-Channel High Dielectric Constant Insulated Gate Field Effect Transistors
Method and Apparatus for Reducing the Power Consumed by a Computer System
Mechanism for Adaptively Adjusting a Direct Current Loadline in a Multi-Core Processor
Active State Link Power Management
Active State Link Power Management
Systems and Methods for Multi-Slotted Power Saving Multiple Polling in Wireless Communications
Method, System, and Apparatus for Dynamically Configuring the Operating Point Utilized for Thermal Management of an Integrated Circuit
Method and Apparatus for Adjusting the Voltage and Frequency to Minimize Power Dissipation in a Multiprocessor System in Response to Compute Load
Method and Apparatus for Limiting Processor Clock Frequency
Method and apparatus of power management of processor
Obscuring Memory Access Patterns
Method for Achieving Fairness in a Network
Providing an Inclusive Shared Cache Among Multiple Core-Cache Clusters
Cantilever on Cantilever Structure
Method and Apparatus for Supporting Scalable Coherence on Many-Core Products Through Restricted Exposure
Weighted Tone Reservation for Ofdm Papr Reduction
Method and System to Increase Concurrency and Control Replication in a Multi-Core Cache Hierarchy
Obscuring Memory Access Patterns
Mechanism for adaptively adjusting a direct current loadline in a multi-core processor
Power Switches Having Positive-Channel High Dielectric Constant Insulated Gate Field Effect Transistors
Method and Apparatus for Supporting Scalable Coherence on Many-Core Products Through Restricted Exposure
Related Assignments
(19)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Feb 22, 1995
From: SINGH, GURBIR; WANG, WEN-HANN; RHODEHAMEL, MICHAEL W.; BAUER, JOHN M.
To: INTEL CORPORATION
Reel/Frame 007352/0114 →
Assignment of Assignor's Interest
Nov 22, 1996
From: NOBLE, JAMES L.; HART, FRANK P.; NGUYEN, DON J.; COOPER, BARNES
To: INTEL CORPORATION
Reel/Frame 008240/0132 →
Assignment of Assignor's Interest
Sep 30, 1997
From: CHUNG, SHINE
To: INTEL CORPORATION
Reel/Frame 008740/0401 →
Assignment of Assignor's Interest
Jan 9, 1998
From: PATTERSON, DAN; PRASAD, BINDI; SINGH, GURBIR; MACWILLIAMS, PETER
To: INTEL CORPORATION
Reel/Frame 008903/0756 →
Assignment of Assignor's Interest
Apr 16, 1998
From: WILSON, JAMES A.; NETTING, ROBERT F.; DESROSIER, PETER
To: INTEL CORPORATION
Reel/Frame 009115/0346 →
Assignment of Assignor's Interest
May 18, 1998
From: HILL, DAVID L.; PRUDVI, CHINNA; BRACHAND, DEREK T.; FISCH, MATTHEW A.
To: INTEL CORPORATION
Reel/Frame 009217/0317 →
Assignment of Assignor's Interest
May 20, 1998
From: CLARK, LAWRENCE T.; BEILEY, MARK A.; HOFFMAN, ERIC J.
To: INTEL CORPORATION
Reel/Frame 009210/0753 →
Assignment of Assignor's Interest
Sep 10, 1998
From: DE, VIVEK K.; YE, YIBIN
To: INTEL CORPORATION
Reel/Frame 009458/0783 →
Assignment of Assignor's Interest
Sep 11, 1998
From: YE, YIBIN; DE, VIVEK K.
To: INTEL CORPORATION
Reel/Frame 009450/0437 →
Assignment of Assignor's Interest
Dec 3, 1998
From: POLE, EDWIN J., II; RUSHFORD, SCOTT R.; SWARTZENDRUBER, ERIC S.; DAI, XIA
To: INTEL CORPORATION
Reel/Frame 009646/0229 →
Assignment of Assignor's Interest
Dec 15, 1998
From: LORTZ, VICTOR B.; RITCHIE, JONATHAN G.
To: INTEL CORPORATION
Reel/Frame 009669/0377 →
Assignment of Assignor's Interest
Feb 18, 1999
From: BACHAND, DEREK; BRUEDER, PAUL; FISCH, MATT
To: INTEL CORPORATION
Reel/Frame 009778/0720 →
Assignment of Assignor's Interest
Feb 19, 1999
From: KHANDEKAR, NARENDRA S.; LENT, DAVID D.; BOGIN, ZOHAR
To: INTEL CORPORATION
Reel/Frame 009770/0697 →
Assignment of Assignor's Interest
Mar 29, 1999
From: BORKAR, SHEKHAR Y.; DE, VIVEK K.; KESHAVARZI, ALI; NARENDRA, SIVA G.
To: INTEL CORPORATION
Reel/Frame 009862/0803 →
Assignment of Assignor's Interest
Apr 29, 1999
From: KURD, NASSER A.; FRODSHAM, R. TIM; WIGHT, E. JEFFREY
To: INTEL CORPORATION
Reel/Frame 009937/0247 →
Assignment of Assignor's Interest
Apr 30, 1999
From: LEE, CHAN; AHJA, HITESH; KRICK, ROBERT F.
To: INTEL CORPORATION
Reel/Frame 009927/0675 →
Assignment of Assignor's Interest
May 24, 1999
From: RANKIN, LINDA J.; GUNTHER, STEPHEN H.; BURTON, EDWARD A.; PIPPIN, JACK D.
To: INTEL CORPORATION
Reel/Frame 009988/0490 →
Assignment of Assignor's Interest
Jun 24, 1999
From: MCDANIEL, BART R.; CLARK, LAWRENCE T.
To: INTEL CORPORATION
Reel/Frame 010046/0585 →
Assignment of Assignor's Interest
Mar 31, 2005
From: BRETERNITZ JR., MAURICIO; HUM, HERBERT; WU, YOUFENG; KIM, SANGWOOK
To: INTEL CORPORATION
Reel/Frame 016445/0656 →