Method and apparatus for limiting processor clock frequency

1. An apparatus comprising:

clock generation logic to generate a clock signal having a clock signal frequency to clock a circuit; and

overclocking prevention logic to prevent operation of the circuit at a frequency greater than a programmable frequency wherein the overclocking prevention logic comprises:

a first plurality of programmable fusible elements programmed with a selected processor clock frequency, the selected processor clock frequency based on the state of each of the first plurality of fusible elements, and

a comparator and a second plurality of programmable fusible elements programmed to identify a maximum processor clock frequency based on the state of each of the second plurality of fusible elements, the comparator to compare the programmed maximum clock frequency to the selected processor clock frequency and to generate a signal indicating whether or not the selected processor clock frequency is greater than the maximum clock frequency.

2. The apparatus according to claim 1 , the overclocking prevention logic further comprising:

a switching device, the switching device to receive outputs from the second plurality of programmable fusible elements and a multi-bit input signal, the switching device to output a signal identifying the selected processor clock frequency.

3. The apparatus according to claim 1 further comprising:

a storage device, the storage device to store the signal indicating whether or not the selected processor clock frequency is greater than the maximum clock frequency.

4. The apparatus according to claim 1 , further comprising:

a clock frequency selection circuit, the clock frequency selection circuit to output signals identifying the selected processor clock frequency.

5. A method comprising:

identifying a programmed clock frequency, the programmed clock frequency based on the state of each fusible element of a first plurality of programmable fusible elements;

comparing a selected clock frequency to the programmed clock frequency, wherein the selected clock frequency is based on the state of each fusible element of a second plurality of programmable fusible elements; and

selecting the lower of the selected clock frequency and the programmed clock frequency to clock a circuit.

6. The method of claim 5 , further comprising:

generating a signal indicating whether or not the selected clock frequency is greater than the programmed clock frequency.

7. An apparatus comprising:

overclocking prevention logic to prevent operation of a circuit at a frequency greater than a programmable clock frequency, the overclocking prevention logic comprising:

a first plurality of fusible elements to determine the programmable clock frequency based on the state of each fusible element of the first plurality of programmable fusible elements,

a second plurality of fusible elements to determine a selected clock frequency based on the state of each fusible element of the second plurality of programmable fusible elements, and

a comparator to compare the programmable clock frequency to a selected processor clock frequency and to generate a signal indicating whether or not the selected processor clock frequency is greater than the programmable clock frequency.

8. The apparatus of claim 7 , the overclocking logic further comprising a switching device to receive outputs from the second plurality of programmable fusible elements and a multi-bit input signal and to output a signal identifying the selected processor clock frequency.

9. The apparatus of claim 7 , further comprising: a storage device to store the signal indicating whether or not the selected processor clock frequency is greater than the programmable clock frequency.

10. The apparatus of claim 7 , further comprising:

a clock frequency selection circuit to output signals identifying the selected processor clock frequency.