Parallel multi-threaded processing
A parallel, multi-threaded processor system and technique for arbitrating command requests is described. The system includes a plurality of microengines, a plurality of shared system resources and a global command arbiter. The global command arbiter uses a command request protocol that is based on the shared system resources and command type to grant or deny a microengine command request for a shared resource.
1. A method for using a parallel, multi-threaded processor system comprising:
processing threads with a plurality of microengines, at least one microengine capable of processing at least two independent threads;
processing commands issued by the microengines using a plurality of system resource interface units that each include at least one commands queue; and
utilizing a global command arbiter including a pointer to store the identity of the a last agent that had a request granted to determine whether a particular microengine command request should be granted.
2. The method of claim 1 wherein each microengine utilizes a FIFO commands register.
3. The method of claim 1 wherein the system resource units include at least one of a core controller, a SDRAM controller, a SRAM controller, a PCI bus interface and an FBUS interface.
4. The method of claim 3 wherein in at least one of the SDRAM controller, the SRAM controller and the FBUS interface utilize three command queues.
5. The method of claim 3 wherein in at least one of the SDRAM controller and the SRAM controller utilize a high priority queue.
6. The method of claim 3 wherein the SRAM controller utilizes a read lock fail queue.
7. The method of claim 3 wherein the PCI bus interface utilizes a single command register.
8. The method of claim 1 , wherein the agent comprises at least one of the following: a microengine and a microengine thread.
9. The method of claim 1 , wherein the threads comprise at least one thread that operates on a packet.
10. A communications system comprising:
at least one Ethernet medium access controller (MAC);
a multithreaded processor, the processor including:
a plurality of microengines for processing a plurality of hardware threads;
at least one of an ASB translator, a PCI bus interface, a SDRAM controller, a SRAM controller, and an bus interface to the Ethernet MAC; and
a global command arbiter including a pointer to store the identity of the a last agent that had a request granted to determine whether a particular command request should be granted.
11. The system of claim 10 further comprising a FIFO commands register for each microengine.
12. The system of claim 10 wherein at least one of the SDRAM controller, the SRAM controller and the FBUS interface includes three command queues.
13. The system of claim 10 wherein at least one of the SDRAM controller and the SRAM controller includes a high priority queue.
14. The system of claim 10 wherein the SRAM controller includes a read lock fail queue.
15. The system of claim 10 wherein the PCI bus interface includes a single command register.
16. The method system of claim 10 , wherein the agent comprises at least one of the following: a microengine and a microengine thread.
17. The method system of claim 10 , wherein the threads comprise at least one thread that operates on a packet received via the at least one Ethernet MAC.
18. A method comprising:
identifying a last programmable unit of a plurality of multiple multi - threaded programmable units within an integrated circuit to have a request granted; and
based, at least in part, on the identifying of the last programmable unit of the plurality of multiple multi - threaded programmable units within the integrated circuit to have a request granted, selecting a different one of the multiple multi - threaded programmable units within the integrated circuit to have a next request granted.
19. The method of claim 18 , wherein the plurality of multiple multi- threaded programmable units within the integrated circuit are associated with a sequence of the multiple multi - threaded programmable units within the integrated circuit; and wherein selecting the one of the multiple multi - threaded programmable units within the integrated circuit to have a next request granted comprises selecting a next one of the multiple multi - threaded programmable units within the integrated circuit in the sequence.
20. The method of claim 18 , further comprising:
selecting a memory access operation issued by the selected one of the multiple multi - threaded programmable units within the integrated circuit.
21. An integrated circuit, comprising:
multiple multi - threaded programmable units in the integrated circuit; and
logic, communicatively coupled to the multiple multi - threaded programmable units, to:
identify a last programmable unit of the plurality of multiple multi - threaded programmable units within the integrated circuit to have a request granted; and
based, at least in part, on the identified last programmable unit of the plurality of multiple multi - threaded programmable units within the integrated circuit to have a request granted, select a one of the multiple multi - threaded programmable units within the integrated circuit to have a next request granted.
22. The integrated circuit of claim 21 , wherein the plurality of multiple multi- threaded programmable units within the integrated circuit are associated with a sequence of the multiple multi - threaded programmable units; and wherein the logic to select the one of the multiple multi - threaded programmable units within the integrated circuit to have a next request granted comprises logic to select a next one of the multiple multi - threaded programmable units in the sequence.
23. The integrated circuit of claim 21 , wherein the logic comprises an arbiter coupled to the multiple multi- threaded programmable units and to a memory controller to a memory shared by the multiple multi - threaded programmable units.
24. The integrated circuit of claim 21 , wherein the logic further comprises logic to:
select a memory access operation issued by the selected one of the multiple multi - threaded programmable units within the integrated circuit.
25. A method for using a parallel, multi- threaded processor system comprising:
processing threads with a plurality of microengines, at least one microengine capable of processing at least two independent threads;
processing commands issued by the microengines using a plurality of system resource interface units that each include at least one commands queue; and
storing an identity of a last agent that had a request granted to determine whether a particular microengine command request should be granted, wherein a pointer is included to store the identity.
26. The method of claim 25 , wherein each microengine utilizes a FIFO commands register.
27. The method of claim 25 , wherein the system resource units include at least one of a core controller, a SDRAM controller, a SRAM controller, a PCI bus interface and an FBUS interface.
28. The method of claim 27 , wherein at least one of the SDRAM controller, the SRAM controller and the FBUS interface utilize three command queues.
29. The method of claim 27 , wherein in at least one of the SDRAM controller and the SRAM controller utilize a high priority queue.
30. The method of claim 27 , wherein the SRAM controller utilizes a read lock fail queue.
31. The method of claim 27 , wherein the PCI bus interface utilizes a single command register.
32. The method of claim 25 , wherein the agent comprises at least one of the following: a microengine and a microengine thread.
33. The method of claim 25 , wherein the threads comprise at least one thread that operates on a packet.
34. A communications system comprising:
at least one Ethernet medium access controller ( MAC ) ;
a multithreaded processor, the processor including:
a plurality of microengines for processing a plurality of hardware threads;
at least one of an ASB translator, a PCI bus interface, a SDRAM controller, a SRAM controller, and an bus interface to the Ethernet MAC; and
a pointer to store an identity of a last agent that had a request granted, the system configured to determine whether a particular command request should be granted.
35. The system of claim 34 further comprising a FIFO commands register for each microengine.
36. The system of claim 34 wherein at least one of the SDRAM controller, the SRAM controller and the FBUS interface includes three command queues.
37. The system of claim 34 wherein at least one of the SDRAM controller and the SRAM controller includes a high priority queue.
38. The system of claim 34 wherein the SRAM controller includes a read lock fail queue.
39. The system of claim 34 wherein the PCI bus interface includes a single command register.
40. The system of claim 34 , wherein the agent comprises at least one of the following: a microengine and a microengine thread.
41. The system of claim 34 , wherein the threads comprise at least one thread that operates on a packet received via the at least one Ethernet MAC.