Method and apparatus for enabling a low power mode for a processor
In accordance with an embodiment of the present invention, a triggering event is initiated to place a processor in a low power state. The processor may or may not flush a cache upon entering the low power state depending on a power status signal. The power status signal may indicated the relative priority of power reduction associated with placing the processor in the low power state without first flushing the cache versus an increase in soft error rate in the cache associated with reducing the voltage in the low power state.
1. An apparatus comprising:
a processor cache memory; and
logic to flush the cache memory upon the processor entering a low power state responsive to an indication that reducing power is a lower priority than a decreased soft error rate.
2. The apparatus of claim 1 wherein the indication that reducing power is a lower priority than a decreased soft error rate responsive to at least one of a) the apparatus being powered by an alternating current source, b) a thermal trip point associated with the apparatus having not been exceeded and c) a requested priority.
3. The apparatus of claim 1 wherein the lower power state is other than a suspend state.
4. The apparatus of claim 3 wherein the logic is responsive to the processor entering a suspend state to flush the processor cache memory regardless of the indication that reducing power is a lower priority than a decreased soft error rate.
5. A processor comprising:
a cache memory to store information;
a core to execute instructions; and
logic responsive to an indication of whether reducing power is a higher or lower priority than a decreased soft error rate.
6. The processor of claim 5 wherein the cache memory includes more than one level of cache memory.
7. The processor of claim 5 wherein the cache memory is to be flushed responsive to an indication that a computer system including the processor is to enter a suspend state.
8. The processor of claim 5 wherein the logic is to determine that the cache memory is to be flushed responsive to an indication that a decreased soft error rate is a higher priority than reducing power.
9. The processor of claim 8 wherein an indication that reducing power is a higher priority than a decreased soft error rate is in response to at least one of a) an indication that a computer system including the processor is being powered by a battery, b) an indication that a thermal trip point has been exceeded, and c) an indication of a request to prioritize power reduction.
10. The processor of claim 9 wherein the indication of whether reducing power is a higher or lower priority than a decreased soft error rate is provided by at least a first power status signal.
11. A method comprising:
receiving an indication of a triggering event associated with a computer system entering a low power state; and
flushing a cache memory if the computer system is to enter a suspend state, or if the computer system is not to enter a suspend state, and it is indicated that a decreased soft error rate is a higher priority than reducing power.
12. The method of claim 11 further comprising:
receiving a power status signal to indicate whether the decreased soft error rate is a higher or lower priority than reducing power.
13. The method of claim 12 wherein
receiving the power status signal includes receiving a power status signal indicating that reducing power is a higher priority than a decreased soft error rate in response to at least one of a) an indication of a battery power source, b) an indication that a thermal trip point has been exceeded, and c) an indication of a requested priority.
14. The method of claim 11 further comprising:
lowering a voltage supplied to the cache memory.
15. The method of claim 14 wherein
lowering the voltage supplied to the cache memory includes lowering the voltage to less than twice the average threshold voltage of a majority of transistors of a processor including the cache memory.
16. A storage device including machine-readable instructions that, if executed by a machine, cause the machine to perform the method of claim 11 .