Offset cancellation and slice adjust amplifier circuit
A method and apparatus to provide slice adjustment and offset cancellation in a high frequency limiting amplifier is described.
1. An apparatus, comprising
a slice adjust circuit coupled to an amplifier input terminal and configured to adjust a slice level such that a signal margin above said slice level is symmetric with the signal margin below said slice level;
an offset cancellation circuit coupled to an amplifier output terminal, said offset cancellation circuit configured to receive an undesired offset signal and feed said signal back to said amplifier input terminal to cancel said undesired offset signal; and
a high impedance buffer circuit coupled to said offset cancellation circuit, said buffer circuit configured to provide high current gain and a high impedance value for said amplifier.
2. An apparatus, comprising:
a slice adjust circuit coupled to an amplifier input terminal and configured to adjust a slice level such that a signal margin above said slice level is symmetric with the signal margin below said slice level;
an offset cancellation circuit coupled to an amplifier output terminal, said offset cancellation circuit configured to receive an undesired offset signal and feed said signal back to said amplifier input terminal to cancel said undesired offset signal; and
wherein said offset cancellation circuit further comprises an emitter follower transistor and a terminating resistor connected to the collector of said emitter follower transistor.
3. The apparatus of claim 2 , wherein said offset cancellation circuit further comprises a current source coupled to said emitter follower transistor.
4. The apparatus of claim 3 , wherein said offset cancellation circuit further comprises a resistor coupled between an emitter terminal of said emitter follower transistor and said current source, said resistor configured to provide RF isolation of said emitter follower transistor.
5. The apparatus of claim 1 , further comprising:
a limiting amplifier; and
a differential amplifier circuit coupled to said offset cancellation circuit and said high impedance buffer circuit, said differential amplifier circuit configured to set a quiescent input voltage for said amplifier.
6. The apparatus of claim 5 , wherein said differential amplifier circuit further comprising a transistor configured to receive an output of said high impedance buffer circuit and a current source coupled to said transistor.
7. The apparatus of claim 5 , further comprising an amplifier bias circuit, said bias circuit configured to provide a bias voltage control signal to said differential amplifier circuit.
8. The apparatus of claim 1 , further comprising an optical transmission medium configured to supply information data signals to said amplifier.
9. An apparatus, comprising:
a limiting amplifier having an input terminal and an output terminal, said limiting amplifier comprising a plurality of amplifier stages;
a slice adjust circuit coupled to said input terminal, said circuit configured to adjust a slice level in response to a temperature measurement of said amplifier;
an offset cancellation circuit coupled to said output terminal, said cancellation circuit configured to generate a signal to voltage compensate an offset associated with said amplifier output and supply said voltage compensating signal to said amplifier input and apply a current bias offset canceling differential to a first stage of said plurality of amplifier stages; and
a high impedance buffer circuit coupled to said offset cancellation circuit, said buffer circuit configured to provide high current gain and a high impedance value.
10. An apparatus, comprising:
a limiting amplifier having an input terminal and an output terminal, said limiting amplifier comprising a plurality of amplifier stages;
a slice adjust circuit coupled to said input terminal, said circuit configured to adjust a slice level in response to a temperature measurement of said amplifier;
an offset cancellation circuit coupled to said output terminal, said cancellation circuit configured to generate a signal to voltage compensate an offset associated with said amplifier output and supply said voltage compensating signal to said amplifier input and apply a current bias offset canceling differential to a first stage of said plurality of amplifier stages; and
wherein said offset cancellation circuit further comprises an emitter follower transistor and a terminating resistor connected to the collector of said emitter follower transistor.
11. The apparatus of claim 10 wherein said offset cancellation circuit further comprises a current source coupled to said emitter follower transistor.
12. The apparatus of claim 11 , wherein said offset cancellation circuit further comprises a resistor coupled between an emitter terminal of said emitter follower transistor and said current source, said resistor configured to provide RF isolation of said emitter follower transistor.
13. The apparatus of claim 9 , further comprising a differential amplifier circuit coupled to said offset cancellation circuit and said high impedance buffer circuit, said differential amplifier circuit configured to set a quiescent input voltage of said amplifier.
14. The apparatus of claim 13 , wherein said differential amplifier circuit further comprising a transistor configured to receive an output of said high impedance buffer circuit and a current source coupled to said transistor.
15. The apparatus of claim 13 , further comprising an amplifier bias circuit, said bias circuit configured to provide a bias voltage control signal to said differential amplifier stage.
16. The apparatus of claim 9 , further comprising an optical transmission medium configured to supply information data signals to said amplifier.