Granted Patent
Utility
US 6,574,738
· Confirmation No. 4160
METHOD AND APPARATUS TO CONTROL PROCESSOR POWER AND PERFORMANCE FOR SINGLE PHASE LOCK LOOP (PLL) PROCESSOR SYSTEMS
|
⬇ PDF
|
Code | Description | Pages | ||
|---|---|---|---|---|---|
| 2002-07-11 | TRNA |
Transmittal of New Application | 2 | View | |
| 2002-07-11 | SPEC |
Specification | 16 | View | |
| 2002-07-11 | CLM |
Claims | 5 | View | |
| 2002-07-11 | ABST |
Abstract | 1 | View | |
| 2002-07-11 | DRW |
Drawings-only black and white line drawings | 8 | View | |
| 2002-07-11 | OATH |
Oath or Declaration filed | 5 | View |
Inventors
Satchit Jain
San Jose, CA
Sung-Soo Cho
Sunnyvale, CA
Attorneys & Agents of Record
Classification
USPC
713/300
G06F1/324
Y02D10/00
G06F1/3203
G06F1/3296
Prosecution
- Examiner
- RAY, GOPAL C
- Art Unit
- 2181
- Docket No.
- 42P7303C
- Confirmation No.
- 4160
Publication
- Pub. No.
- US20020188884A1
- Pub. Date
- 2002-12-12
Patent Term Adjustment
-1days
from
INTEL CORPORATION
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded 2014-05-14
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this application's details
Quick Facts
- Patent No.
- US 6,574,738
- App. No.
- 10/194,617
- Filed
- 2002-07-11
- Granted
- 2003-06-03
- Pub. No.
- US20020188884A1
- Examiner
- RAY, GOPAL C
- Art Unit
- 2181
- PTA
- -1 days
External Links