Active state link power management
A distributed power management system for a bus architecture or similar communications network. The system supports multiple low power states and defines entry and exit procedures for maximizing energy savings and communication speed.
1. A method comprising:
detecting a first power state transition timing in a first device;
detecting a first power state transition timing tolerance in the first device;
assigning a value related to the first power state to the first device; and
storing the value in a storage device.
2. The method of claim 1 , further comprising:
detecting a first power state transition timing in a second device;
detecting a first power state transition timing tolerance in the second device; and
assigning a value related to the first power state to the second device.
3. The method of claim of claim 2 , wherein the value assigned to the first device is based upon a first device tolerance compared to a path latency to the second device.
4. The method of claim 1 , further comprising:
detecting a second power state transition timing in the first device;
detecting a second power state transition timing tolerance in the first device; and
assigning a value related to the second power state to the first device.
5. The method of claim 4 , wherein the value enables the first and second power state to be entered for the first device.
6. The method of claim 1 , wherein the value enables the first power state to be entered for the first device.
7. The method of claim 1 , wherein the value disables the first power state to be entered for the first device.
8. A machine-readable storage medium that provides instructions, which when executed by a machine cause the machine to perform operations comprising:
detecting a first power state transition timing in a first device;
detecting a first power state transition timing tolerance in the first device; and
assigning a value related to the first power state to the first device.
9. The machine-readable medium of claim 8 , further comprising:
detecting a first power state transition timing in a second device;
detecting a first power state transition timing tolerance in the second device;
assigning a value related to the first power state to the second device; and
storing the value in a storage device.
10. The machine-readable storage medium of claim 9 , wherein the value assigned to the first device is based upon a first device tolerance compared to a path latency to the second device.
11. The machine-readable storage medium of claim 8 , further comprising:
detecting a second power state transition timing in the first device;
detecting a second power state transition timing tolerance in the first device; and
assigning a value related to the second power state to the first device.
12. The machine-readable storage medium of claim 11 , wherein the value enables the first and second power state to be entered for the first device.
13. The machine-readable storage medium of claim 8 , wherein the value enables the first power state to be entered for the first device.
14. The machine-readable storage medium of claim 8 , wherein the value disables the first power state to be entered for the first device.