Method of manufacturing semiconductor device
View Patent ↗A semiconductor device manufacturing method wherein a via-hole is formed in an second inter-layer insulating film covering a lower layer wiring, throughout a surface of which are then formed a barrier film made of Ta (tantalum) and a Cu (copper) film sequentially, after which, first an unnecessary part of the Cu film is removed by a CMP (Chemical Mechanical Polishing) method using such a polishing liquid to which hydrogen peroxide is added by 1.5 weight-percent or more (first polishing step) and then an unnecessary part of the barrier film is removed by a CMP method for using a polishing liquid to which hydrogen peroxide is added by 0.09-1.5 weight-percent and applying a pressure of 4-10 Psi (pounds per square inch) on the barrier film (second polishing step).
1. A method of manufacturing a semiconductor device comprising:
forming a lower layer wiring;
forming an inter-layer insulating film to cover therewith said lower layer wiring;
a via-hole forming step for forming a via-hole in said inter-layer insulating film to expose said lower layer wiring at a bottom of said via-hole;
a barrier film forming step for forming a barrier film throughout a surface including said via-hole;
a conductive film forming step for forming a conductive film on said barrier film;
a first polishing step for polishing and removing said conductive film on said barrier film until said barrier film is exposed by a chemical mechanical polishing method using a first polishing liquid to achieve said conductive film having a higher polishing rate than said barrier film;
a second polishing step for removing said barrier film on said inter-layer insulating film by a chemical mechanical polishing method using a second polishing liquid to achieve said conductive film having a lower polishing rate than said barrier film, to leave said conductive film as non-removed only in said via-hole via said barrier film, thus forming a via-plug; and
forming an upper layer wiring on said inter-layer insulating film after performing said second polishing step, thus single-damascene-interconnecting said lower layer wiring and said upper layer wiring through said via-plug.
2. The method of manufacturing a semiconductor device according to claim 1 , wherein said second polishing step is performed with a pressure of 4-10 Psi (Pounds per square inch) applied on said barrier film on said inter-layer insulating film.
3. The method of manufacturing a semiconductor device according to claim 1 , wherein said barrier film comprises tantalum-based metal and said conductive film comprises copper-based metal.
4. The method of manufacturing a semiconductor device according to claim 1 , wherein said lower layer wiring and said upper layer wiring comprise respectively copper-based metal.
5. A method of manufacturing a semiconductor device comprising:
forming a lower layer wiring;
forming an inter-layer insulating film to cover therewith said lower layer wiring;
a via-hole forming step for forming a via-hole in said inter-layer insulating film to expose said lower layer wiring at a bottom of said via-hole;
a via-hole forming step for forming a via-hole in said inter-layer insulating film to expose said lower layer wiring at a bottom of said via-hole;
a barrier film forming step for forming a barrier film throughout a surface including said via-hole;
a conductive film forming step for forming a conductive film on said barrier film;
a first polishing step for polishing and removing said conductive film on said barrier film until said barrier film is exposed by a chemical mechanical polishing method using a first polishing liquid to which hydrogen peroxide is added by 1.5 weight-percent or more;
a second polishing step for removing said barrier film on said inter-layer insulating film by a chemical mechanical polishing method using a second polishing liquid to which hydrogen peroxide is added by 0.09-1.5 weight-percent, to leave said conductive film as non-removed only in said via-hole via said barrier film, thus forming a via-plug, wherein said second polishing liquid has concentration of hydrogen peroxide that is lower than concentration of hydrogen peroxide contained in said first polishing liquid; and
forming an upper layer wiring on said inter-layer insulating film after performing said second polishing step, thus single-damascene-interconnecting said lower layer wiring and said upper layer wiring through said via-plug.
6. The method of manufacturing a semiconductor device according to claim 5 , wherein said second polishing step is performed with a pressure of 4-10 Psi applied on said barrier film on said inter-layer insulating film.
7. The method of manufacturing a semiconductor device according to claim 5 , where said barrier film comprises tantalum-based metal and said conductive film comprises copper-based metal.
8. The method of manufacturing a semiconductor device according to claim 5 , wherein said lower layer wiring and said upper layer wiring comprise respectively copper-based metal.
9. A method of manufacturing a semiconductor device comprising:
forming a lower layer wiring;
forming an inter-layer insulating film to cover therewith said lower layer wiring;
a via-hole forming step for forming a via-hole in said inter-layer insulating film to expose said lower layer wiring at a bottom of said via-hole;
a barrier film forming step for forming a barrier film throughout a surface including said via-hole;
a conductive film forming step for forming a conductive film on said barrier film;
a first polishing step for polishing and removing said conductive film on said barrier film until said barrier film is exposed by a chemical mechanical polishing method using a polishing liquid to which hydrogen peroxide is added by 1.5 weight-percent or more;
a second polishing step for removing said barrier film on said inter-layer insulating film by a chemical mechanical polishing method using a polishing liquid containing no hydrogen peroxide, to leave said conductive film as non-removed only in via-hole via said barrier film, thus forming a via-plug; and
forming a upper wiring layer on said inter-layer insulating film, thus interconnecting said lower layer wiring and said upper layer wiring through said via-plug.
10. The method of manufacturing a semiconductor device according to claim 9 , wherein said second polishing step is performed with a pressure of 4-10 Psi applied on said barrier film on said inter-layer insulating film.
11. The method of manufacturing a semiconductor device according to claim 9 ,
wherein said step of forming said upper layer wiring on said inter-layer insulating film is performed after said second polishing step, thus single-damascene-interconnecting said lower layer wiring and said upper layer wiring through said via-plug.
12. The method of manufacturing a semiconductor device according to claim 9 , where said barrier film comprises tantalum-based metal and said conductive film comprises copper-based metal.
13. The method of manufacturing a semiconductor device according to claim 9 , wherein said lower layer wiring and said upper layer wiring comprise respectively copper-based metal.