IP Library Granted Patent US 6,885,530
Granted Patent B2
US 6,885,530 · App. 10/166,876 · Granted Apr 26, 2005

Power limiting time delay circuit

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,885,530
App. No.
10/166,876
Granted
Apr 26, 2005
Kind
B2
Abstract

A power limiting circuit for power supply that is controlled by a power supply control module includes a shunt regulator having a reference input operatively connected to a voltage input that receives a voltage representative of the power supply control module connected thereto. The shunt regulator is biased on when the voltage at the reference input increases above a reference voltage established at the voltage input. A transistor is operatively connected to the shunt regulator and to an output operatively connected to the power supply control module and has a voltage that is representative of voltage operating the power supply control module. The transistor is biased on from the shunt regulator such that the shunt regulator and transistor form a latch when the voltage at the output reduces below an off voltage level to turn off the power supply, dropping the input voltage, and restarting the power supply in a restart cycle.

Claims (33)

1. A power limiting circuit for a power supply controlled by a power supply control module comprising:

a voltage (Vcomp) input operatively connected to the power supply control module for receiving a voltage indicative of a power supply error;

a voltage (Vdd) output operatively connected to the power supply control module and an operating voltage for the power supply control module;

a three terminal integrated circuit shunt regulator having a cathode, an anode, and a reference input operatively connected to said voltage (Vcomp) input, said shunt regulator being biased on when the voltage to the reference input increases above a reference voltage established at the voltage (Vcomp) input;

a bipolar transistor operatively connected to said shunt regulator and being biased on from the shunt regulator such that said shunt regulator and transistor form a latch wherein the voltage at the (Vdd) output will reduce below a (Vdd) off voltage level to turn off the power supply, dropping the (Vcomp) input voltage and switching the power supply to a new cycle.

2. A power limiting circuit according to claim 1 and further comprising a time delay circuit operatively connected to said shunt regulator for delaying the biasing on of the shunt regulator.

3. A power limiting circuit according to claim 2 wherein said time delay circuit comprises a resistor and capacitor operatively connected to said reference input of the shunt regulator.

4. A power limiting circuit according to claim 1 wherein said transistor comprises a bipolar transistor.

5. A power limiting circuit according to claim 4 , wherein said bipolar transistor has an emitter connected to said output representative of the operating voltage of the power supply control module.

6. A power limiting circuit according to claim 1 and further comprising a bulk DC voltage input of the power supply and a resistor divider circuit operatively connected to the reference input of the shunt regulator for sensing bulk DC voltage of the power supply and establishing a voltage threshold for the shunt regulator.

7. A power limiting circuit according to claim 6 wherein as bulk voltage increases, the voltage required to bias the shunt regulator on decreases.

8. A method of controlling a power supply comprising the steps of:

sensing an input voltage to a power control circuit that is representative of the output power supply error; and

if an excess output power threshold is exceeded within a specified period of time, then maintaining the power supply in a normal operating condition, but switching the power supply to a new cycle with an output power less than a specified limit if the excess output power threshold is exceeded beyond the specified period of time.

9. A method according to claim 8 and further comprising the step of continuing the new cycle as long as the excess output power threshold remains.

10. A method according to claim 9 and further comprising the step of continuing a normal operating condition of the power supply when the excess output power beyond the output power threshold is removed.

11. A method according to claim 8 and further comprising the step of establishing a voltage threshold at an input connected to a power supply control module by measuring input bulk DC voltage corresponding to a rectified AC input voltage such that the voltage at the input increases when there is an increase in load and a decrease in AC input voltage.

12. A method according to claim 8 wherein the input corresponds to an output voltage for a power supply control module error amplifier.

13. A method according to claim 8 and further comprising the step of pulling below an off voltage level when there is an excess load for initiating a new cycle.

14. A method according to claim 8 and further comprising the steps of forming a latch within the power control circuit using a shunt regulator and transistor such that the voltage at the output will reduce below the off voltage level to turn off the power supply, dropping the input voltage and switching the power supply to a new cycle.

15. A method according to claim 14 and further comprising the step of starting the power supply when excess power is removed.

16. A method according to claim 14 and further comprising the step of maintaining the power supply in a continuous new cycle when excess power remains.

17. A method of controlling a power supply comprising the steps of:

sensing an input voltage at a (Vcomp) input of a power control circuit that is connected to a power supply control module;

biasing on a shunt regulator having a reference input that is operatively connected to the (Vcomp) input when the voltage to the reference input increases above a reference voltage; and

biasing on a transistor that forms a latch with the shunt regulator such that as transistor current increases, the shunt regulator turns on more wherein the voltage at a (Vdd) output will reduce below a (Vdd) off voltage level and turn off the power supply, dropping the (Vcomp) input voltage and switching the power supply in a new cycle.

18. A method according to claim 17 and further comprising the step of delaying the shunt regulator from turning on by providing a time constant from a capacitor and resistor combination operatively connected to the reference input of the shunt regulator.

19. A method according to claim 17 and further comprising the step of sensing input bulk voltage and as bulk voltage increases, reducing the amount of voltage required to turn on the shunt regulator.

20. A method according to claim 17 and further comprising the step of continuing the new cycle as long as the excess output power threshold remains.

21. A method according to claim 20 and further comprising the step of continuing a normal operating condition of the power supply when the excess output power beyond the output power threshold is removed.

22. A method according to claim 20 and further comprising the step of establishing a voltage threshold at the (Vcomp) input by measuring input bulk DC voltage corresponding to a rectified AC input voltage such that the voltage at (Vcomp) increases when there is an increase in load and a decrease in AC input voltage.

23. A method according to claim 17 wherein the output to the power supply at the (Vcomp) input corresponds to an output to a power supply control module error amplifier.

24. A method according to claim 17 and further comprising the step of pulling below a (Vdd) off voltage level at the (Vdd) output when there is an excess load.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 25, 2021
From: STMICROELECTRONICS INTERNATIONAL N.V.
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 058298/0235 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 13, 2021
From: STMICROELECTRONICS, INC.
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 057791/0514 →