Patent Assignment
Reel/Frame 057791/0514
Assignment of Assignor's Interest
Recorded: 2021-10-13
Pages: 10
Assignor
STMICROELECTRONICS, INC.
Executed: 2021-10-07
Assignee
STMICROELECTRONICS INTERNATIONAL N.V.
39, CHEMIN DU CHAMP DES FILLES, 1228 PLAN-LES-OUATES, GENEVA, SWITZERLAND
Covered Properties
(52)
Device to Control the Power Supply in an Integrated Circuit Comprising Electrically Programmable Non-Volatile Memory Elements
Thermally-Enhanced Ball Grid Array Package Structure and Method
Method for Providing a Redistribution Metal Layer in an Integrated Circuit
Power Limiting Time Delay Circuit
Protection of an Integrated Circuit Against Electrostatic Discharges and Other Overvoltages
Power Limiting Time Delay Circuit
Semiconductor Device Having an Integrated, Self-Regulated Pwm Current and Power Limiter and Method
Application:
11/172,515 →
Publication:
US 2007/0013361
System for Providing a Redistribution Metal Layer in an Integrated Circuit
Thermally-Enhanced Ball Grid Array Package Structure and Method
Semiconductor Device Having an Integrated, Self- Regulated Pwm Current and Power Limiter and Method
Method for Providing a Redistribution Metal Layer in an Integrated Circuit
Transistor Having a Stressed Body
Application:
13/454,570 →
Publication:
US 2013/0277747
Semiconductor Device with an Inclined Source/Drain and Associated Methods
Multi-Fin Finfet Device Including Epitaxial Growth Barrier on Outside Surfaces of Outermost Fins and Related Methods
Finfet Device with Isolated Channel
Facet-Free Strained Silicon Transistor
Method of Forming a Fully Substrate-Isolated Finfet Transistor
Method of Making a Semiconductor Device Using Spacers for Source/Drain Confinement
Method of Making a Semiconductor Device Using a Dummy Gate
Application:
13/906,789 →
Publication:
US 2014/0353716
METHOD TO CO-INTEGRATE SiGe AND Si CHANNELS FOR FINFET DEVICES
Finfet with Multiple Concentration Percentages
Method to Induce Strain in Finfet Channels from an Adjacent Region
Method for the Formation of a Finfet Device Having Partially Dielectric Isolated Fin Structure
Multi-Layer Strained Channel Finfet
Transistor Having a Stressed Body
Fully Substrate-Isolated Finfet Transistor
Multi-Fin Finfet Device Including Epitaxial Growth Barrier on Outside Surfaces of Outermost Fins and Related Methods
Method of Using a Sacrificial Gate Structure to Make a Metal Gate Finfet Transistor
Method to Induce Strain in Finfet Channels from an Adjacent Region
Method for the Formation of a Finfet Device Having Partially Dielectric Isolated Fin Structure
Method of Making a Semiconductor Device Using Spacers for Source/Drain Confinement
METHOD TO CO-INTEGRATE SiGe AND Si CHANNELS FOR FINFET DEVICES
Method of Making a Semiconductor Device Using a Dummy Gate
Facet-Free Strained Silicon Transistor
Method to Form Localized Relaxed Substrate by Using Condensation
Finfet Device Having a Partially Dielectric Isolated Fin Structure
Method to Induce Strain in Finfet Channels from an Adjacent Region
Multi-Fin Finfet Device Including Epitaxial Growth Barrier on Outside Surfaces of Outermost Fins and Related Methods
Method of Making a Semiconductor Device Using a Dummy Gate
Fully Substrate-Isolated Finfet Transistor
Self-Aligned Silicon Germanium Finfet with Relaxed Channel Region
Method to Form Localized Relaxed Substrate by Using Condensation
Method to Co-Integrate Sige and Si Channels for Finfet Devices
Fully Substrate-Isolated Finfet Transistor
Self-Aligned Silicon Germanium Finfet with Relaxed Channel Region
Method of Making a Semiconductor Device Using a Dummy Gate
Application:
15/979,326 →
Publication:
US 2018/0261674
Method to Induce Strain in Finfet Channels from an Adjacent Region
Multi-Fin Finfet Device Including Epitaxial Growth Barrier on Outside Surfaces of Outermost Fins and Related Methods
METHOD TO CO-INTEGRATE SiGe AND Si CHANNELS FOR FINFET DEVICES
Method to Induce Strain in Finfet Channels from an Adjacent Region
Multi-Fin Finfet Device Including Epitaxial Growth Barrier on Outside Surfaces of Outermost Fins and Related Methods
Method to Induce Strain in Finfet Channels from an Adjacent Region
Related Assignments
(7)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Apr 24, 2012
From: LIU, QING; LOUBET, NICOLAS; KHARE, PRASANNA
To: STMICROELECTRONICS, INC.
Reel/Frame 028098/0187 →
Assignment of Assignor's Interest
Aug 21, 2012
From: LIU, QING; KHARE, PRASANNA; LOUBET, NICOLAS
To: STMICROELECTRONICS, INC.
Reel/Frame 028820/0390 →
Assignment of Assignor's Interest
Aug 21, 2012
From: LIU, QING; KHARE, PRASANNA; LOUBET, NICOLAS
To: STMICROELECTRONICS, INC.
Reel/Frame 028821/0859 →
Assignment of Assignor's Interest
Jan 22, 2013
From: LOUBET, NICOLAS; KHARE, PRASANNA; LIU, QING
To: STMICROELECTRONICS, INC.
Reel/Frame 029672/0773 →
Assignment of Assignor's Interest
Jun 4, 2021
From: STMICROELECTRONICS S.A.
To: STMICROELECTRONICS, INC.
Reel/Frame 056445/0948 →
Assignment of Assignor's Interest
Jun 4, 2021
From: STMICROELECTRONICS S.A.
To: STMICROELECTRONICS, INC.
Reel/Frame 056445/0804 →
Assignment of Assignor's Interest
Oct 25, 2021
From: STMICROELECTRONICS INTERNATIONAL N.V.
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 058298/0235 →