IP Library Granted Patent US 9,905,662
Granted Patent B2
US 9,905,662 · App. 14/976,781 · Granted Feb 27, 2018

Method of making a semiconductor device using a dummy gate

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Quick Facts
Patent No.
US 9,905,662
App. No.
14/976,781
Granted
Feb 27, 2018
Kind
B2
Abstract

A method of making a semiconductor device includes forming a fin mask layer on a semiconductor layer, forming a dummy gate over the fin mask layer, and forming source and drain regions on opposite sides of the dummy gate. The dummy gate is removed and the underlying fin mask layer is used to define a plurality of fins in the semiconductor layer. A gate is formed over the plurality of fins.

Claims (49)

1. A method of making a semiconductor device comprising:

forming a fin mask layer on a semiconductor layer, the fin mask layer having a first portion and a second portion;

forming a dummy gate over the first portion of the fin mask layer;

exposing a surface of the semiconductor layer by removing portions of the semiconductor layer on opposite sides of the dummy gate;

forming source and drain regions on the surface of the semiconductor layer on opposite sides of the dummy gate;

removing the dummy gate;

forming a plurality of fins in the semiconductor layer using the second portion of the fin mask layer;

removing the second portion of the fin mask layer, the first portion of the fin mask layer remaining; and

forming a single gate over the plurality of fins, the forming of the gate including:

forming a dielectric layer on the first portion of the fin mask layer; and

forming a polysilicon layer on the dielectric layer.

2. The method according to claim 1 wherein forming the dummy gate comprises forming the dummy gate so that the second portion of the fin mask layer extend outwardly away from the dummy gate.

3. The method according to claim 2 further comprising forming a dummy gate mask layer over the dummy gate.

4. The method according to claim 3 further comprising removing the second portion of the fin mask layer that extend outwardly away from the dummy gate using the dummy gate mask layer.

5. The method according to claim 1 wherein forming the dummy gate comprises forming an oxide layer and a polysilicon layer thereover.

6. The method according to claim 1 further comprising forming sidewall spacers on the dummy gate.

7. The method according to claim 1 wherein the removing of the portions of the semiconductor layer on opposite sides of the dummy gate includes forming source and drain recesses and forming the source and drain regions in the respective source and drain recesses.

8. The method according to claim 1 further comprising removing the second portion of the fin mask layer before forming the gate.

9. The method according to claim 1 wherein forming the source and drain regions comprises forming raised source and drain regions.

10. The method according to claim 1 wherein forming the source and drain regions comprises forming the source and drain regions of a different material than the semiconductor layer.

11. A method for making a semiconductor device comprising:

forming a fin mask layer on a semiconductor layer;

forming a dummy gate over a first portion of the fin mask layer so that a second portion of the fin mask layer extend away from the dummy gate;

forming a dummy gate mask layer over the dummy gate;

forming a plurality of fins in the semiconductor layer using the second portion of the fin mask layer; and

removing the second portion of the fin mask layer that extend away from the dummy gate using the dummy gate mask layer, the first portion of the fin mask layer remaining;

removing upper portions of the semiconductor layer on opposite sides of the dummy gate to define source and drain recesses, lower portions of the semiconductor layer remain;

forming source and drain regions in the source and drain recesses on the lower portions of the semiconductor layer;

forming sidewalls adjacent to the dummy gate and the first portion of the fin mask layer; and

forming a single gate over the plurality of fins between the sidewalls, the forming of the gate including:

forming a dielectric layer on the first portion of the fin mask layer; and

forming a polysilicon layer on the dielectric layer.

12. The method according to claim 11 wherein forming the dummy gate comprises forming an oxide layer and a polysilicon layer thereover.

13. The method according to claim 11 further comprising removing the second portion of the fin mask layer before forming the gate.

14. The method according to claim 11 wherein forming the source and drain regions comprises forming raised source and drain regions.

15. The method according to claim 11 wherein forming the source and drain regions comprises forming the source and drain regions of a different material than the semiconductor layer.

16. A method of making a semiconductor device comprising:

forming a fin mask layer on a semiconductor layer having a first portion and a second portion;

forming a dummy gate over the first portion of the fin mask layer;

forming source and drain regions on opposite sides of the dummy gate;

removing the dummy gate;

forming a plurality of fins in the semiconductor layer using the second portion of the fin mask layer; and

forming a unitary gate over the plurality of fins, the forming of the unitary gate over the plurality of fins including:

forming a dielectric layer on the first portion of the fin mask layer; and

forming a polysilicon layer on the dielectric layer.

17. The method according to claim 16 wherein forming the dummy gate comprises forming the dummy gate so that the second portion of the fin mask layer extend outwardly away from the dummy gate.

18. The method according to claim 17 further comprising forming a dummy gate mask layer over the dummy gate.

19. The method according to claim 18 further comprising removing the second portions of the fin mask layer that extend outwardly from the dummy gate using the dummy gate mask layer.

20. The method according to claim 16 wherein forming the dummy gate comprises forming an oxide layer and a polysilicon layer thereover.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 25, 2021
From: STMICROELECTRONICS INTERNATIONAL N.V.
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 058298/0235 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 13, 2021
From: STMICROELECTRONICS, INC.
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 057791/0514 →