Method to induce strain in finFET channels from an adjacent region
View Patent ↗Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.
1. A method for making a strained three-dimensional feature on a substrate, the method comprising:
forming a first semiconductor layer in a strained state at a surface of a substrate;
cutting the first semiconductor layer to relieve strain in the first semiconductor layer and form a strain-relieved structure;
depositing, after the cutting, a material adjacent the strain-relieved structure to restrict expansion and contraction of the strain-relieved structure;
growing a second semiconductor layer in a strained state adjacent to a surface of the strain-relieved structure; and
forming the strained three-dimensional feature in the second semiconductor layer.
2. The method of claim 1 , wherein the growing comprises epitaxial growth of the second semiconductor layer on the surface of the strain-relieved structure.
3. The method of claim 1 , wherein the thickness of the first semiconductor layer is between 10 nm and 60 nm.
4. The method of claim 3 , wherein the thickness of the second semiconductor layer is between 10 nm and 60 nm.
5. The method of claim 1 , wherein the first semiconductor layer comprises SiGe or SiC.
6. The method of claim 5 , further comprising forming the first semiconductor layer with a gradient in Ge or C content in a direction perpendicular to the surface of the substrate.
7. The method of claim 5 , wherein the second semiconductor layer comprises Si.
8. The method of claim 1 , wherein the three-dimensional feature comprises a fin for a finFET device.
9. The method of claim 8 , wherein the cutting comprises etching a pattern for the fin through the first semiconductor layer.
10. The method of claim 8 , wherein the first semiconductor layer comprises SiGe or SiC and the second semiconductor layer comprises Si.
11. The method of claim 8 , further comprising forming a gate structure for a finFET at a center of the fin in the second semiconductor layer.
12. The method of claim 8 , wherein forming the first semiconductor layer comprises epitaxially growing the first semiconductor layer.
13. The method of claim 8 , wherein forming the second semiconductor layer comprises epitaxially growing the second semiconductor layer.
14. The method of claim 8 , wherein cutting the first semiconductor layer comprise at least one etching process.
15. The method of claim 8 , wherein a lateral width of the fin is determined by the material adjacent the strain-relieved structure.
16. The method of claim 8 , wherein the fin has a width between 5 nm and 30 nm.
17. A method for making strained-channel finFET structure on a substrate comprising:
forming a strain-inducing base structure adjacent to a fin of the finFET structure, the strain-inducing base structure comprising a first semiconductor material having a first lattice constant that is mismatched to a second lattice constant of the fin, and the fin comprising a second semiconductor material that is strained by the strain-inducing base structure; and
forming a constraining material adjacent the strain-inducing base structure, the constraining material having a Young's modulus higher than a Young's modulus of the strain-inducing base structure.
18. The method of claim 17 , wherein the first semiconductor material comprises SiGe or SiC.
19. The method of claim 18 , wherein a Ge or C content of the SiGe or SiC is between 10% and 25%.
20. The method of claim 18 , wherein a Ge or C content of the SiGe or SiC is between 25% and 40%.
21. The method of claim 18 , wherein the first semiconductor material has a gradient in Ge or C concentration in a direction perpendicular to an interfacial surface between the strain-inducing base structure and the fin.
22. The method of claim 17 , wherein the second semiconductor material comprises Si.
23. The method of claim 17 , wherein a thickness of the first semiconductor material is between 10 nm and 60 nm.
24. The method of claim 17 , wherein a thickness of the second semiconductor material is between 10 nm and 60 nm.
25. The method of claim 17 , wherein the fin has a width between 5 nm and 30 nm.
26. The method of claim 17 , further comprising forming a gate structure at a medial region of the fin.
27. The method of claim 17 , wherein the Young's modulus of the constraining material is at least twice a value of the Young's modulus of the strain-inducing base structure.
28. A method for making semiconductor device comprising:
forming a strained-channel finFET structure on a substrate by at least
forming a fin,
forming a strain-inducing base structure adjacent to the fin, the strain-inducing base structure comprising a first semiconductor material having a first lattice constant that is mismatched to a second lattice constant of the fin, the fin comprising a second semiconductor material that is strained by the strain-inducing base structure, and
forming a constraining material adjacent the strain-inducing base structure, the constraining material having a Young's modulus higher than a Young's modulus of the strain-inducing base structure.
29. The method of claim 28 , wherein the first semiconductor material comprises SiGe.
30. The method of claim 19 , wherein a Ge content of the SiGe is between 10% and 40%.
31. The method of claim 19 , wherein the first semiconductor material has a gradient in Ge concentration in a direction perpendicular to an interfacial surface between the strain-inducing base structure and the fin.
32. The method of claim 29 , wherein the first semiconductor material comprises SiC.
33. The method of claim 32 , wherein a C content of the SiC is between 10% and 40%.
34. The method of claim 32 , wherein the first semiconductor material has a gradient in C concentration in a direction perpendicular to an interfacial surface between the strain-inducing base structure and the fin.
35. The method of claim 28 , wherein a thickness of the first semiconductor material is between 10 nm and 60 nm, and a thickness of the second semiconductor material is between 10 nm and 60 nm.