IP Library Granted Patent US 11,587,928
Granted Patent B2
US 11,587,928 · App. 17/093,528 · Granted Feb 21, 2023

Method to induce strain in finFET channels from an adjacent region

Inventors: Pierre Morin (Kessel-Lo, BE); Nicolas Loubet (Guilderland, NY)
Assignee: Bell Semiconductor, LLC
H01L27/0924H01L29/1054H01L29/16H01L29/165H01L29/1608H01L29/66636H01L29/66795H01L29/785H01L29/7843H01L29/7848H01L29/7849
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Quick Facts
Patent No.
US 11,587,928
App. No.
17/093,528
Granted
Feb 21, 2023
Kind
B2
Abstract

Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

Claims (30)

1. A device, comprising:

a substrate having a pedestal;

a fin-shaped structure over the pedestal of the substrate, the fin-shaped structure including a first layer of a first semiconductor material and a second layer of a second material, the first layer stacked on the second layer with the second layer between the first layer and the substrate in a first direction, and the second material different from a material of the substrate;

two constraining structures, one on each of two sides of the fin-shaped structure in a second direction that crosses the first direction, wherein each constraining structure is adjacent to all of the pedestal, all of the second layer, and a lower portion of the first layer in the second direction; and

a gate structure contacting at least the first layer of the fin-shaped structure.

2. The device of claim 1 wherein each constraining structure has a Young's modulus greater than 50 Gpa.

3. The device of claim 1 wherein each constraining structure is a nitride material.

4. The device of claim 1 wherein the gate structure includes a gate dielectric layer and a conductive layer, the gate dielectric layer positioned on the two constraining structures and between the conductive layer and the first layer of the fin-shaped structure.

5. The device of claim 1 wherein the second material of the second layer has a lattice mismatch with the first semiconductor material of the first layer.

6. The device of claim 5 wherein the second material of the second layer has a lattice mismatch with a material of the substrate.

7. The device of claim 5 wherein the first semiconductor material is silicon and the second material is silicon germanium.

8. The device of claim 7 wherein the first layer is an epitaxial silicon layer.

9. The device of claim 7 wherein the second layer has a germanium concentration of about 25% and has a thickness of about 40 nm in the first direction.

10. The device of claim 7 wherein the second layer has a germanium concentration of about 30% and has a thickness of about 30 nm in the first direction.

11. A device, comprising:

a substrate of a first material at a first surface of the substrate, the substrate having a pedestal;

a first structure of a second material on the pedestal of the substrate, the second material having a lattice mismatch with the first material;

a second structure of a third material on the first structure, the third material having a lattice mismatch with the second material;

two constraining structures, one on each of two sides of the first structure, wherein each constraining structure is adjacent to all of the pedestal, all of the first structure, and a lower portion of the second structure; and

a gate structure adjacent to the second structure.

12. The device of claim 11 , each constraining structure has a Young's modulus greater than 50 Gpa.

13. A method, comprising:

forming a substrate having a pedestal;

forming a first fin-shaped structure over the pedestal of the substrate, the first fin-shaped structure having a first material that includes a lattice mismatch with the first surface of the substrate;

forming two constraining structures, each laterally adjacent to one of two sides of the first fin-shaped structure;

forming a second fin-shaped structure on the first fin-shaped structure, the second fin-shaped structure having a second material that includes a lattice mismatch with the first material of the first fin-shaped structure, wherein each constraining structure is laterally adjacent to all of the pedestal, all of the first fin-shaped structure, and a lower portion of the second fin-shaped structure; and

forming a gate structure contacting the second fin-shaped structure.

14. The method of claim 13 wherein the forming the second fin-shaped structure includes:

forming the second fin-shaped structure within a space at least partially defined by the two constraining structures; and

etching each constraining structure down to a height that is above an interface between the first fin-shaped structure and the second fin-shaped structure.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 25, 2021
From: STMICROELECTRONICS INTERNATIONAL N.V.
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 058298/0235 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 13, 2021
From: STMICROELECTRONICS, INC.
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 057791/0514 →