Method to co-integrate SiGe and Si channels for finFET devices
A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level.
1. A device, comprising:
a substrate;
an array of n-type fins extending from a surface of the substrate, the n-type fins including a first semiconductor material having n-type conductivity;
an array of p-type fins extending from the surface of the substrate, the array of p-type fins being adjacent to the array of n-type fins, the p-type fins including a second semiconductor material that is different from the first semiconductor material, the second semiconductor material having p-type conductivity; and
an insulator on the surface of the substrate, the insulator separating adjacent fins from one another.
2. The device of claim 1 , wherein each of the p-type fins further includes the first semiconductor material.
3. The device of claim 1 , wherein each of the p-type fins include an upper portion and a lower portion made of different materials, the upper portion being the second semiconductor material.
4. The device of claim 1 , wherein each of the n-type fins and the p-type fins includes one or more of Si, SiC, SiGe, GaAs, and AlGaAs materials.
5. The device of claim 1 , wherein the first semiconductor material comprises SiGe and the second semiconductor material comprises Si and lacks Ge.
6. A device, comprising:
a substrate including a first portion that extends outward from a first surface of the substrate;
a first fin including the first portion of the substrate and a second portion that extends outward from a second surface of the first portion, the second portion being a first semiconductor material; and
a second fin extending outward from the first surface of the substrate, the second fin being a second semiconductor material.
7. The device of claim 6 , wherein the first fin and the second fin include one or more of Si, SiC, SiGe, GaAs, and AlGaAs materials.
8. The device of claim 7 , wherein the first semiconductor material comprises SiGe and the second semiconductor material comprises Si and lacks Ge.
9. The device of claim 6 , wherein the first semiconductor material has p-type conductivity.
10. The device of claim 6 , wherein the second semiconductor material has n-type conductivity.
11. The device of claim 6 , further including an insulator on the first surface of the substrate, the insulator being between the first fin and the second fin.
12. The device of claim 6 , further including a gate overlying the first fin and the second fin, the gate being transverse to the first and second fins.
13. A method comprising:
forming a first fin including:
forming a first portion from a substrate, the first portion extending outward from a first surface of the substrate; and
forming a second portion extending outward from a second surface of the first portion, the second portion being of a first semiconductor material; and
forming a second fin of a second semiconductor material, the second fin extending outward from the first surface of the substrate.
14. The method of claim 13 , wherein the first fin and the second fin include one or more of Si, SiC, SiGe, GaAs, and AlGaAs materials.
15. The method of claim 13 , wherein the first semiconductor material has p-type conductivity.
16. The method of claim 13 , wherein the second semiconductor material has n-type conductivity.
17. The method of claim 13 , wherein forming the first fin includes:
forming a layer of the first semiconductor material on the substrate;
defining a fin feature by lithographically patterning a resist mask; and
etching the first fin in the layer of the first semiconductor material.
18. The method of claim 17 , wherein the lithographically patterning and etching includes at least a portion of a sidewall image transfer process.
19. The method of claim 17 , further including depositing a first insulator over the first fin.
20. The method of claim 19 , further including:
removing a portion of the first insulator;
removing the resist mask;
depositing a second insulator;
planarizing the second insulator; and
forming a hard mask layer on the second insulator after the planarizing.