IP Library Granted Patent US 9,219,133
Granted Patent B2
US 9,219,133 · App. 13/905,586 · Granted Dec 22, 2015

Method of making a semiconductor device using spacers for source/drain confinement

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Quick Facts
Patent No.
US 9,219,133
App. No.
13/905,586
Granted
Dec 22, 2015
Kind
B2
Abstract

A method of making a semiconductor device includes forming a first spacer for at least one gate stack on a first semiconductor material layer, and forming a respective second spacer for each of source and drain regions adjacent the at least one gate. Each second spacer has a pair of opposing sidewalls and an end wall coupled thereto. The method includes filling the source and drain regions with a second semiconductor material while the first and second spacers provide confinement.

Claims (20)

1. A method of making a semiconductor device comprising:

forming a first spacer for at least one gate stack on a first semiconductor material layer;

forming a respective second spacer for each of source and drain regions in the first semiconductor layer and adjacent the at least one gate stack, each second spacer comprising a pair of opposing sidewalls and an end wall coupled thereto;

forming at least one fin for each pair of source and drain regions;

etching the at least one fin for each pair of source and drain regions to form source and drain recesses;

shaping the source and drain recesses to have an inclined extension adjacent the at least one gate stack; and

filling the source and drain recesses with a second semiconductor material while the first and second spacers provide confinement.

2. The method according to claim 1 , wherein the etching and filling are performed in a same processing chamber.

3. The method according to claim 1 , wherein the first and second spacers comprise a nitride.

4. The method according to claim 1 , wherein the first and second semiconductor materials are different semiconductor materials so that a stress is imparted to a channel region under the at least one gate stack.

5. The method according to claim 4 , wherein the first semiconductor material comprises silicon, and the second semiconductor material comprises silicon and germanium.

6. The method according to claim 1 , wherein the first semiconductor layer comprises a silicon on insulator (SOI) wafer.

7. A method of making a semiconductor device comprising:

forming a first nitride spacer for at least one gate stack on a first semiconductor material layer;

forming a respective second nitride spacer for each of source and drain regions in the first semiconductor layer and adjacent the at least one gate stack, each second nitride spacer comprising a pair of opposing sidewalls and an end wall coupled thereto;

forming at least one fin for each pair of source and drain regions;

etching the at least one fin for each pair of source and drain regions to form source and drain recesses;

shaping the source and drain recesses to have an inclined extension adjacent the at least one gate stack; and

filling the source and drain recesses with a second semiconductor material while the first and second nitride spacers provide confinement.

8. The method according to claim 7 , wherein the etching and filling are performed in a same processing chamber.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 25, 2021
From: STMICROELECTRONICS INTERNATIONAL N.V.
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 058298/0235 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 13, 2021
From: STMICROELECTRONICS, INC.
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 057791/0514 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 10, 2013
From: LOUBET, NICOLAS; MORIN, PIERRE
To: STMICROELECTRONICS, INC.
Reel/Frame 030578/0885 →