Methods and apparatus for clock and data recovery using transmission lines
View Patent ↗A data receiver circuit includes a transmission line to generate the appropriate timing for clock and data recovery. The transmission line receives a reference signal, and propagates the reference signal through at least two segments of predetermined lengths. The transmission line is configured with a first tab to extract, from the first predetermined length, a first delayed signal, and a second tab to extract, from the second predetermined length, a second delayed signal. A sampling circuit generates samples, at a first time period, from an input signal and the first delayed signal. The sampling circuit also generates samples, at a second time period, from the input signal and the second delayed signal. A capacitance control device to adjust the capacitance of the transmission line is disclosed. The data receiver circuit and the transmission line may be both fabricated on an integrated circuit, or the transmission line may be implemented external to the integrated circuit chip, such as on a package housing of the integrated circuit chip or on a printed circuit board for which the integrated circuit chip is mounted.
1. A data receiver circuit comprising:
a transmission line comprising a plurality of segments of predetermined lengths, said transmission line to receive a reference signal and to propagate said reference signal for the predetermined lengths, said transmission line further comprising:
a first tab to extract, from a first segment of said transmission line, a first delayed signal and;
a second tab to extract, from a second segment of said transmission line, a second delayed signal, wherein each tab is situated at the end of each segment of said transmission line;
a sampling circuit, coupled to said transmission line, to receive a serial bit stream and to generate samples of said serial bit stream at times specified by said first delayed signal and at times specified by said second delayed signal, wherein a sampling rate is based on said predetermined lengths of the first and second segments of said transmission line;
a phase detector to detect a phase difference between said reference signal at an input to said transmission line and said reference signal at an output of said transmission line;
a filter, coupled to said phase detector, to receive said phase difference and to generate a value in accordance with a loop filter parameter; and
a capacitance control device, coupled to said transmission line and coupled to receive said value, to adjust the capacitance of said transmission line.
2. The circuit as set forth in claim 1 , wherein said reference signal comprises a clock signal.
3. The circuit as set forth in claim 1 , wherein said phase detector, filter and capacitance control device operate continuously in a digital delay lock loop.
4. The circuit as set forth in claim 1 , wherein said phase detector, filter and capacitance control device operate only at circuit power-up to adjust the capacitance of said transmission line.
5. The circuit as set forth in claim 1 , further comprising an integrated circuit chip comprising said data receiver circuit and said transmission line.
6. The circuit as set forth in claim 1 , wherein said sampling circuit comprises an integrated circuit chip, and said transmission line is implemented external to said integrated circuit chip.
7. The circuit as set forth in claim 6 , wherein said transmission line is implemented on a package housing of said integrated circuit chip.
8. The circuit as set forth in claim 6 , wherein said transmission line is implemented on a printed circuit board on which said integrated circuit chip is mounted.
9. A method for recovering a clock and serial bit stream at a receiver, said method comprising the steps of:
receiving a reference signal;
propagating said reference signal over a transmission line;
extracting, from a first segment of a predetermined length of said transmission line, a first delayed signal;
extracting, from a second segment of a predetermined length of said transmission line, a second delayed signal;
receiving a serial bit stream;
generating samples of said serial bit stream at times specified by said first delayed signal;
generating samples of said serial bit stream at times specified by said second delayed signal, wherein a sampling rate is based on said predetermined lengths of the first and second segments of said transmission lines;
detecting a phase difference between said reference signal at an input to said transmission line and said reference signal at an output of said transmission line;
generating a value for said phase difference in accordance with a loop filter parameter; and
adjusting the capacitance of said transmission line in accordance with said value.
10. The method as set forth in claim 9 , wherein said reference signal comprises the clock signal.
11. The method as set forth in claim 9 , wherein the steps of detecting a phase difference, generating a value for said phase difference, and adjusting the capacitance of said transmission line are performed continuously in a digital delay lock loop.
12. The method as set forth in claim 9 , wherein the steps of detecting a phase difference, generating a value for said phase difference, and adjusting the capacitance of said transmission line are performed only at circuit power-up to adjust the capacitance of said transmission line.
13. The method as set forth in claim 9 , further comprising the step of fabricating said receiver and said transmission line on an integrated circuit chip.
14. The method as set forth in claim 9 , further comprising the steps of:
fabricating said receiver on an integrated circuit chip; and
fabricating said transmission line external to said integrated circuit chip.
15. The method as set forth in claim 14 , wherein the step of fabricating said transmission line external to said integrated circuit chip comprises the step of fabricating said transmission line on a package housing of said integrated circuit chip.
16. The method as set forth in claim 14 , wherein the step of fabricating said transmission line external to said integrated circuit chip comprises the step of fabricating said transmission line on a printed circuit board for which said integrated circuit chip is mounted.