Efficient column redundancy techniques
View Patent ↗The present invention relates to a system and method adapted to increase memory cell and memory architecture design yield. The present invention includes memory architecture having a decoder and a multi-bank memory. The decoder is adapted to decode addresses. The multi-bank memory interacts with the decoder, wherein the multi-bank memory includes at least one output data bit adapted to complete a word for a failing bank in the multi-bank memory.
1. A memory device comprising:
a multi-bank memory;
a multiplexer adapted to access failing bits in said multi-bank memory;
a sense amplifier adapted to be accessed when said multiplexer is selected; and
at least one transmission gate adapted to be activated by multiplexer signals.
2. The memory device of claim 1 , including a routing channel interfacing with at least said sense amplifier and adapted to route signals to said multiplexer.
3. The memory device of claim 1 , wherein said at least one transmission gate is further adapted to pass signals to said sense amplifier.
4. The memory device of claim 1 comprising a shifter block having at least one input data bit and at least one output data bit.
5. The memory device of claim 4 wherein said shifter block shifts out at least one of said failing bits when said multiplexer is selected.
6. The memory device of claim 5 wherein said multiplexer is a failing multiplexer.
7. The memory device of claim 6 wherein said shifter block passes said at least one input data bit directly to said at least one output data bit when said failing multiplexer is not selected.
8. The memory device of claim 5 wherein said multiplexer is a failing multiplexer.
9. The memory device of claim 8 wherein said shifter block passes said at least one input data bit directly to said output data bit when said failing multiplexer is not selected.
10. The memory device of claim 1 comprising a channel router routing m multiplexer signals.
11. A memory architecture comprising:
a synchronous controlled global element;
a self-timed local element having at least one multi-bank memory, said local element comprising:
at least one multiplexer adapted to access failing bits in said multi-bank memory and adapted to interface with said synchronous controlled global element;
a sense amplifier;
at least one said transmission gate adapted to be activated by multiplexer signals; and
said multi-bank memory comprising at least one redundant bank having at least one output data bit adapted to complete a word for a failing bank in said multi-bank memory.
12. The memory architecture of claim 11 , wherein said sense amplifier is adapted to be accessed when said multiplexer is selected.
13. The memory architecture of claim 11 , wherein said local element further comprises a routing channel interfacing with at least said sense amplifier and adapted to route signals to said multiplexer.
14. The memory architecture device of claim 11 , wherein said at least one transmission gate is adapted to pass signals to said sense amplifier.
15. The memory device of claim 11 comprising a shifter block having at least one input data bit and at least one output data bit.
16. The memory device of claim 15 wherein said shifter block shifts out at least one of said failing bits when said multiplexer is selected.
17. The memory device of claim 11 wherein said channel router routes m multiplexer signals.