Power grid and bump pattern with reduced inductance and resistance
View Patent ↗Disclosed are novel methods and apparatus for efficiently providing power buses and bump patterns with reduced inductance and/or resistance. In an embodiment, an apparatus is disclosed. The apparatus includes a plurality of power and ground bus pairs. Each power and ground bus pair may have a power bus and a ground bus. The apparatus further includes a first power bus from a first pair of the plurality of power and ground bus pairs. The first power bus may include a plurality of power bumps. The apparatus also includes a first ground bus from the first pair of the plurality of power and ground bus pairs. The first ground bus may include a plurality of ground bumps. Each of the plurality of power/ground bumps may be substantially equidistance from any immediately neighboring ground bump of the first ground bus.
1. An apparatus comprising:
a first power bus having a first set of power bumps;
a first ground bus having a first set of around bumps, the first ground bus adjacent to the first power bus and forming a first bus pair with the first power bus;
a second power bus having a second set of power bumps;
a second ground bus having a second set of around bumps, the second ground bus adjacent to the second power bus and forming a second bus pair with the second power bus; and
a wire extending the width of the first power bus on a side of the first power bus opposite from the first ground bus.
2. The apparatus of claim 1 wherein the first power bus and the first ground bus are located as close as possible to each ocher without causing an electrical short.
3. The apparatus of claim 1 wherein the apparatus provides reduction in inductance associated with the power and the ground buses.
4. The apparatus of claim 1 wherein the first power bus includes a plurality of wires coupled between the power bumps.
5. The apparatus of claim 1 wherein the first ground bus includes a plurality of wires coupled between the ground bumps.
6. The apparatus of claim 1 wherein the wire reduces at least one of a resistance and inductance associated with the first power bus.
7. The apparatus of claim 1 wherein the distance between the first power bus and the first ground bus is 30 microns.
8. An apparatus comprising:
a first power bus having a first set of power bumps;
a first around bus having a first set of around bumps, the first around bus adjacent to the first power bus and forming a first bus pair with the first power bus;
a second power bus having a second set of power bumps;
a second around bus having a second set of ground bumps, the second ground bus; adjacent to the second power bus and forming a second bus pair with the second power bus; and
a wire extending the width of the first ground bus on a side of the first around bus opposite from the first power bus.
9. The apparatus of claim 8 wherein the first power bus includes a plurality of wires coupled between the power bumps.
10. The apparatus of claim 8 wherein the first around bus includes a plurality of wires coupled between the ground bumps.
11. The apparatus of claim 8 wherein the wire reduces a resistance associated with the first ground bus.
12. The apparatus of claim 11 wherein each power bump is substantially equidistant from any immediately neighboring ground bump of the first ground bus and each ground bump is substantially equidistant from any immediately neighboring power bump.
13. The apparatus of claim 8 wherein an individual bump is removed without increasing a voltage drop associated with the bus that would have included the removed bump.
14. The apparatus of claim 8 wherein the power and ground buses are adjusted to a selected resistance value without changing a location of the plurality of the power and ground bumps.
15. The apparatus of claim 8 wherein the plurality of power bumps contain lead.
16. The apparatus of claim 8 wherein the plurality of ground bumps contain lead.
17. The apparatus of claim 12 wherein the distance associated with the substantially equidistant bumps is determined by the semiconductor process utilized to provide the apparatus.
18. The apparatus of claim 13 wherein the removed bump is located over an alpha sensitive circuit.
19. The apparatus of claim 13 wherein at least one metal from the bus is widened to compensate for a voltage drop associated with removing the bump.
20. An apparatus comprising:
a first power bus including a first set of power bumps having a diagonal pattern;
a first ground bus including a first set of around bumps, the first ground bus adjacent to the first power bus and forming a first bus pair with the first power bus;
a second power bus including a second set of power bumps having a diagonal pattern; and
a second ground bus including a second set of ground bumps, the second ground bus adjacent to the second power bus and forming a second bus pair with the second power bus;
a wire extending the width of the first ground bus on a side of the first ground bus opposite from the first power bus.
21. The apparatus of claim 20 wherein the first power bus and the first ground bus are located as close as possible to each other without causing an electrical short.
22. The apparatus of claim 20 wherein the apparatus provides reduction in inductance associated with the power and the ground buses.
23. The apparatus of claim 20 wherein the first power bus includes a plurality of wires coupled between the power bumps.
24. The apparatus of claim 20 wherein each power bump is substantially equidistant from any immediately neighboring ground bump of the first ground bus and each ground bump is substantially equidistant from any immediately neighboring power bump.
25. The apparatus of claim 20 wherein the power and ground buses are adjusted to a selected resistance value without changing a location of the plurality of the power and ground bumps.
26. The apparatus of claim 21 wherein the distance between the first power bus and the first ground bus is 30 microns.
27. The apparatus of claim 23 wherein the first ground bus includes a plurality of wires coupled between the ground bumps.
28. The apparatus of claim 24 wherein the distance associated with the substantially equidistant bumps is determined by the semiconductor process utilized to provide the apparatus.