IP Library Granted Patent US 7,139,332
Granted Patent B2
US 7,139,332 · App. 10/184,766 · Granted Nov 21, 2006

Quadrature receiver sampling architecture

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,139,332
App. No.
10/184,766
Granted
Nov 21, 2006
Kind
B2
Abstract

Quadrature receiver sampling architecture. A signal ADC performs analog to digital conversion for both I and Q streams. An analog MUX selects the appropriate I and the Q baseband analog input streams for input to the ADC at the appropriate time. A digital filter may also be employed to compensate for any introduced delay between the samples of the I and Q channel when seeking to recover the symbols that have been transmitted to a communication receiver that employs this quadrature receiver architecture and/or signal processing. In one embodiment, if an ADC is clocked at a rate of substantially twice the sample rate of the I and Q channels, there will be a one-half sample clock delay between the digital I and digital Q data at the output of the ADC. This delay is then removed before the demodulator processes the input signals to recover the transmitted symbols.

Claims (62)

1. A communication receiver, comprising:

an analog front-end that is operable to receive an analog I stream and an analog Q stream;

a digital processing unit that is communicatively coupled to the analog front-end;

wherein the analog front-end includes a multiplexor and a single analog to digital convener that operate cooperatively to perform alternative digital sampling of the analog I stream and the analog Q stream thereby convening the analog I stream and the analog Q stream into a digital I stream and a digital Q stream; and

the digital processing unit is operable to perform decimation and de-rotation of a digital sample of the digital I stream and the digital Q stream, the rotation being introduced during the analog to digital conversion of the analog I stream and the analog Q stream, the digital processing unit includes a digital signal processor, wherein the digital signal processor performs mathematical operations on the digital I stream and the digital Q stream to compensate for delay that occurs during the analog to digital conversion of the analog I stream and the analog Q stream thereby performing the de-rotation of the digital sample of the digital I stream and the digital Q stream.

2. The communication receiver of claim 1 , further comprising a radio frequency interface that is operable to extract the analog I stream and the analog Q stream from a received analog signal.

3. The communication receiver of claim 1 , wherein a selector of the multiplexor and the single analog to digital convener being clocked at a frequency that is substantially twice a digital sampling frequency of the analog I stream and the analog Q stream.

4. The communication receiver of claim 1 , wherein a selector of the multiplexor being clocked a first frequency that is substantially twice a digital sampling frequency of the analog I stream and the analog Q stream; and

the single analog to digital convener being clocked at a second frequency that is substantially twice the digital sampling frequency of the analog I stream and the analog Q stream.

5. The communication receiver of claim 1 , wherein the analog front-end further comprises a sample and hold element that is communicatively coupled to the multiplexor.

6. The communication receiver of claim 5 , wherein the analog I stream and the analog Q stream are provided to the multiplexor;

an output of the multiplexor is provided to the sample and hold element; and

an output of the sample and hold element is provided to the single analog to digital converter.

7. The communication receiver of claim 5 , wherein the analog front-end further comprises at least one additional sample and hold element; and

wherein the analog I stream is provided to the sample and hold element;

the analog Q stream is provided to the at least one additional sample and hold element;

outputs from the sample and hold element and the at least one additional sample and hold element are provided to the multiplexor; and

an output of the multiplexor is provided to the single analog to digital converter.

8. The communication receiver of claim 1 , wherein the communication receiver comprises at least one of a base station receiver, a mobile receiver, a set top box, a tower receiver, a mobile unit, and an high definition television (HDTV) set top box receiver.

9. The communication receiver of claim 8 , wherein at least one of the base station receiver and the tower receiver comprises a wireless tower.

10. The communication receiver of claim 8 , wherein at least one of the set top box and the HDTV set top box receiver comprises a local satellite dish.

11. The communication receiver of claim 1 , wherein the communication receiver is contained within a transceiver, the transceiver also comprises a communication transmitter.

12. The communication receiver of claim 2 , wherein the analog signal is received via a wireless communication channel.

13. A satellite communication system, comprising:

a local satellite dish that is operable to receive an analog signal transmitted from a satellite via a wireless communication channel; and

a set top box, communicatively coupled to the local satellite dish via a coaxial cable, that receives the analog signal received by the local satellite dish;

wherein the set top box includes an analog front-end and a digital processing unit, the analog front-end includes a radio frequency interface;

the analog front-end is operable to receive the analog signal transmitted from the satellite and to extract an analog I stream and an analog Q stream therefrom;

the digital processing unit is communicatively coupled to the analog front-end;

the analog front-end includes a multiplexor and a single analog to digital converter that operate cooperatively to perform alternative digital sampling of the analog I stream and the analog Q stream thereby converting the analog I stream and the analog Q stream into a digital I stream and a digital Q stream; and

the digital processing unit is operable to perform decimation and de-rotation of a digital sample of the digital I stream and the digital Q stream, the rotation being introduced during the analog to digital conversion of the analog I stream and the analog Q stream; wherein the digital processing unit includes:

a digital signal processor, a delay element, and a half band interpolating filter;

the delay provided by the delay element is substantially comparable to a time comprises a duration that is substantially comparable to a time required to perform a half band interpolating filtering; and

wherein the delay element and the half band interpolating filter operate cooperatively to compensate for delay that occurs during the analog to digital conversion of the analog I stream and the analog Q stream thereby performing the de-rotation of the digital sample of the digital I stream and the digital Q stream.

14. The satellite communication system of claim 13 , wherein the analog front-end further comprises a radio frequency interface that is operable to extract the analog I stream and the analog Q stream from the received analog signal.

15. The satellite communication system of claim 13 , wherein the analog front-end further comprises a sample and hold element that is communicatively coupled to the multiplexor.

16. A communication receiver, comprising:

an analog front-end that is operable to receive an analog I stream and an analog Q stream;

a digital processing unit that is communicatively coupled to the analog front-end;

wherein the analog front-end includes a multiplexor and a single analog to digital convener that operate cooperatively to perform alternative digital sampling of the analog I stream and the analog Q stream thereby convening the analog I stream and the analog Q stream into a digital I stream and a digital Q stream; and

the digital processing unit is operable to perform decimation and de-rotation of a digital sample of the digital I stream and the digital Q stream, the rotation being introduced during the analog to digital conversion of the analog I stream and the analog Q stream, wherein the digital processing unit includes:

a digital signal processor, a delay element, and the half band interpolating filter;

the delay provided by the delay element is substantially comparable to a time includes a duration that is substantially comparable to a time required to perform the half band interpolating filtering; and

wherein the delay element and the half band interpolating filter operate cooperatively to compensate for any delay that occurs during the analog to digital conversion of the analog I stream and the analog Q stream thereby performing the de-rotation of the digital sample of the digital I stream and the digital Q stream.

17. The communication receiver of claim 16 , further comprising a radio frequency interface that is operable to extract the analog I stream and the analog Q stream from a received analog signal.

18. The communication receiver of claim 16 , wherein a selector of the multiplexor and the single analog to digital convener being clocked at a frequency that is substantially twice a digital sampling frequency of the analog I stream and the analog Q stream.

19. The communication receiver of claim 16 , wherein a selector of the multiplexor being clocked a first frequency that is substantially twice a digital sampling frequency of the analog I stream and the analog Q stream; and

the single analog to digital convener being clocked at a second frequency that is substantially twice the digital sampling frequency of the analog I stream and the analog Q stream.

20. The communication receiver of claim 16 , wherein the analog front-end further comprises a sample and hold element that is communicatively coupled to the multiplexor.

21. The communication receiver of claim 20 , wherein the analog I stream and the analog Q stream are provided to the multiplexor;

an output of the multiplexor is provided to the sample and hold element; and

an output of the sample and hold element is provided to the single analog to digital converter.

22. The communication receiver of claim 20 , wherein the analog front-end further comprises at least one additional sample and hold element; and

wherein the analog I stream is provided to the sample and hold element;

the analog Q stream is provided to the at least one additional sample and hold element;

outputs from the sample and hold element and the at least one additional sample and hold element are provided to the multiplexor; and

an output of the multiplexor is provided to the single analog to digital converter.

23. The communication receiver of claim 16 , wherein the communication receiver comprises at least one of a base station receiver, a mobile receiver, a set top box, a tower receiver, a mobile unit, and an high definition television (HDTV) set top box receiver.

24. The communication receiver of claim 23 , wherein at least one of the base station receiver and the tower receiver comprises a wireless tower.

25. The communication receiver of claim 23 , wherein at least one of the set top box and the HDTV set top box receiver comprises a local satellite dish.

26. The communication receiver of claim 16 , wherein the communication receiver is contained within a transceiver, the transceiver also comprises a communication transmitter.

27. The communication receiver of claim 17 , wherein the analog signal is received via a wireless communication channel.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →