IP Library Granted Patent US 7,346,724
Granted Patent B1
US 7,346,724 · App. 10/186,910 · Granted Mar 18, 2008

Enabling multiple ATA devices using a single bus bridge

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Quick Facts
Patent No.
US 7,346,724
App. No.
10/186,910
Granted
Mar 18, 2008
Kind
B1
Abstract

Embodiments of the invention include a bus bridge that is capable of communicating with more than one MSC device coupled to it. In some embodiments, the bridge includes a LUN processor that translates different LUN numbers received from the bus into different addresses and LUNs for devices connected to the bridge. The bridge masks the fact that multiple MSC devices are coupled to it by reporting to the host that only a single device having multiple LUNs are coupled to the bridge.

Claims (11)

1. A USB (Universal Serial Bus) to ATA/ATAPI (AT Attachment/ATA Packet Interface) bridge, comprising:

a first transceiver configured to communicate with a host over a USB bus;

a second transceiver configured to communicate with a first group of ATA/ATAPI devices over a first ATA bus, each of the first group of ATA/ATAPI devices having a port that is directly connected to the first ATA bus; and

a routing circuit coupled to the first and second transceivers, the routing circuit configured to route signals between the first ATA bus and the host USB bus;

wherein the routing circuit is configured to total a number of LUNs for all of the first group of ATA/ATAPI devices and report the total to the host, where at least one of the first group of ATA/ATAPI devices has more than one LUN.

2. The bridge of claim 1 , wherein the routing circuit causes signals from the ATA bus to appear to the host as if they come from one of the first group of ATA/ATAPI devices.

3. The bridge of claim 2 , wherein the routing circuit is structured to route signals to the first group of ATA/ATAPI devices based on a Logical Unit Number (LUN) table stored in the routing circuit.

4. The bridge of claim 1 , wherein the routing circuit includes functions relating LUNs of the first group of ATA/ATAPI devices to LUNs on to the host bus.

5. The bridge of claim 3 , wherein the routing circuit is structured to decode a reported LUN passed from the host bus into an actual LUN and an address of one of the first group of ATA/ATAPI devices.

6. The bridge of claim 1 , wherein the second transceiver is configured to communicate with a second group of ATA/ATAPI devices over a second ATA bus, each of the second group of ATA/ATAPI devices having a port that is directly connected to the second ATA bus.

7. The bridge of claim 1 , wherein at least one of the first group of ATA/ATAPI devices comprises more than one LUN.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 16, 2025
From: MONTEREY RESEARCH LLC
To: SOUTHFORK IP HOLDINGS LLC
Reel/Frame 071299/0161 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2002
From: CASTLEBERRY, JAMES E.
To: CYPRESS SEMICONDUCTOR CORP.
Reel/Frame 013074/0249 →