Three dimensional integrated device
View Patent ↗A device integration method and integrated device. The method includes the steps of polishing surfaces of first and second workpieces each to a surface roughness of about 5-10 Å. The polished surfaces of the first and second workpieces are bonded together. A surface of a third workpiece is polished to the surface roughness. The surface of the third workpiece is bonded to the joined first and second workpieces. The first, second and third workpieces may each be a semiconductor device having a thin material formed on one surface, preferably in wafer form. The thin materials are polished to the desired surface roughness and then bonded together. The thin materials may each have a thickness of approximately 1-10 times the surface non-planarity of the material on which they are formed. Any number of devices may be bonded together, and the devices may be different types of devices or different technologies.
1. An integrated structure, comprising:
a first element having a plurality of first metallic contact structures;
a second element comprising a plurality of second metallic contact structures, a substantial portion of second element being removed by at least one of grinding and polishing;
a first oxide layer disposed on a surface of said first element, said first oxide layer having a first polished surface with a surface roughness in a surface roughness range;
a second oxide layer disposed on a surface of said second element, said second oxide layer having a second polished surface with a surface roughness in said range of surface roughness; and
an interconnection formed between said at least one of said first metallic contact structures and at least one of said second metallic contact structures,
wherein said first oxide layer is directly bonded to said second oxide layer through said first and second polished surfaces without application of temperature and with a bond strength sufficient to permit removal of said portion of said second element after bonding said first and second oxide layers.
2. A structure as recited in claim 1 , comprising:
said first and second polished surfaces having a surface roughness in a range of about 5-15 Å.
3. A structure as recited in claim 1 , comprising:
said first and second polished surfaces having a surface roughness in a range of about 5-10 Å.
4. A structure as recited in claim 1 , comprising:
said first and second polished surfaces having a surface roughness of no more than about 5 Å.
5. A structure as recited in claim 1 , comprising:
an opening, formed through said second element, said first and second oxide layers, and a portion of said first element, to which a first one of said plurality of first metallic contact structures is exposed; and
said interconnection being farmed in said opening and in contact with said first one of said plurality of first metallic contact structures.
6. A structure as recited in claim 1 , wherein:
said second element comprises a substrate; and
a portion of said substrate is removed to leave a remaining portion of said second element.
7. A structure as recited in claim 6 , comprising:
substantially all of said substrate being removed.
8. A structure as recited in claim 1 , wherein:
said first and second elements comprise respective first and second semiconductor devices; and
said first and second semiconductor devices are of different technologies.
9. A structure as recited in claim 1 , wherein:
said first and second oxide layers each comprises a material having a dielectric constant in the range of approximately 1-3 and a thermal conductivity in the range of approximately 1-10 W/cmK.
10. A structure as recited in claim 1 wherein each of said first and second oxide layers comprises a silicon oxide.
11. A structure as recited in claim 1 ,
wherein said first oxide layer is directly bonded to said second oxide layer through said first and second polished surfaces without application of temperature or pressure during bonding.
12. A structure as recited in claim 1 , wherein:
said first element comprises a first material;
said first plurality of metallic contact structures extend above said first material; and
said first oxide layer is disposed on said first plurality of metallic contact structures and said first material.
13. A structure as recited in claim 12 , wherein:
said first plurality of metallic contact structures extend above said first material by a distance; and
said first oxide layer has a thickness no more than to times said distance.
14. A structure as recited in claim 12 , wherein:
said second oxide layer comprises a second material;
said second plurality of metallic contact structures extend above said second material; and
said second layer is disposed on said second plurality of metallic contact structures and said second material.
15. A structure as recited claim 1 , wherein said first and second oxide layers comprise first and second bonding layers, respectively.
16. A structure as recited in claim 1 , wherein each of said first and second metallic contact structures consists essentially of a metal material.
17. A structure as recited in claim 1 , comprising:
said first oxide layer directly bonded to said second oxide layer through said first and second polished surfaces by placing said first and second polished surfaces in contact without application of pressure.
18. An integrated structure, comprising:
a first element;
a second element having a first semiconductor device formed in a substrate, a substantial portion of said substrate being removed by at least one of grinding and polishing;
a first bonding layer, having a first polished surface, disposed on a top surface of said first element;
a second bonding layer, having a second polished surface, disposed on a top surface of said first semiconductor device; and
said first bonding layer directly bonded to said second bonding layer without application of temperature and with a strength sufficient to permit removal of said portion of said substrate after bonding said first and second bonding layers.
19. A structure a recited in claim 18 , comprising:
a first plurality of metal contact structures disposed in said first element;
a second plurality of metal contact structures disposed in said second element; and
an interconnection formed between one said first metal contact structures and one of said second metal contact structures.
20. A structure as recited in claim 18 , comprising:
said first and second bonding layers having respective first and second surfaces polished to a surface roughness in a range of about 5-15 Å,
said first and second surfaces being bonded together.
21. A structure as recited in claim 18 , comprising:
said first and second bonding layers having respective first and second surfaces polished to a surface roughness in a range of about 5-10 Å,
said first and second surfaces being bonded together.
22. A structure as recited in claim 18 , comprising:
said first and second bonding layers having respective first and second surfaces polished to a surface roughness of no more than about 5 Å,
said first and second surfaces being bonded together.
23. A structure as recited in claim 18 , wherein each of said first and second bonding layers comprises a silicon oxide layer.
24. A structure as recited in claim 18 , comprising:
a first contact structure in said first element;
a second contact structure in said second element;
an opening, formed through said second element, said first and second bonding layers, and a portion of said first element, to which said first contact structure is exposed; and
an interconnection being formed in said opening and in contact with said first and second contact structures.
25. A structure as recited in claim 24 , wherein each of said first and second contact structures consists essentially of a metal material.
26. A structure as recited in claim 18 , comprising:
substantially all of said substrate being removed.
27. A structure as recited in claim 18 , wherein said first element comprises a semiconductor device, said semiconductor devices in said first and second elements being of different technologies.
28. A structure as recited in claim 18 , wherein:
said first and second bonding layers each comprises a material having a dielectric constant in the range of approximately 1-3 and a thermal conductivity in the range of approximately 1-10 W/cmK.
29. A structure as recited in claim 18 ,
wherein said first oxide layer is directly bonded to said second oxide layer through said first and second polished surfaces without application of temperature or pressure during bonding.
30. A structure as recited in claim 18 , comprising:
said first bonding layer directly bonded to said second bonding layer through said first and second polished surfaces by placing said first and second polished surfaces in contact without application of pressure.
31. An integrated structure, comprising:
a first element having a first surface polished to a surface roughness of no more than 15 Å;
a second element having a second surface to which at least one of grinding and polishing operation has been performed, and a third surface polished to a surface roughness of no more than 15 Å;
wherein said first surface is bonded in direct contact with said third surface at about room temperature with a bond strength sufficient to permit at least one of grinding and polishing of said second surface after bonding said first and third surfaces.
32. A structure as recited in claim 31 , comprising:
a first metal contact structure disposed in said first element;
a second metal contact structure disposed in said second element; and
an interconnection formed between said first and second metal contact structures.
33. A structure as recited in claim 31 , comprising:
said first and third surfaces having a surface roughness in a range of about 5-15 Å.
34. A structure as recited in claim 31 , comprising:
said first and third surfaces having a surface roughness in a range of about 5-10 Å.
35. A structure as recited in claim 31 , comprising:
said first and third surfaces having a surface roughness in a range of no more than about 5 Å.
36. A structure as recited in claim 31 , wherein each of said first and third surfaces comprises a surface of a silicon oxide layer.
37. A structure as recited in claim 31 , comprising:
a first contact structure in said first element;
a second contact structure in said second element;
an opening, formed through said second element and a portion of said first element, to which said first contact structure is exposed; and
an interconnection being formed in said opening and in contact with said first and second contact structures.
38. A structure as recited in claim 37 , wherein each of said first and second contact structures consists essentially of a metal material.
39. A structure as recited in claim 31 , wherein:
said second element comprises a substrate; and
substantially all of said substrate is removed.
40. A structure as recited in claim 31 , wherein:
said first element comprises a first semiconductor device,
said second element comprises a second semiconductor device; and
said first and second semiconductor devices are of different technologies.
41. A structure as recited in claim 31 , wherein:
said first and third surfaces each comprises a surface of a material having a dielectric constant in the range of approximately 1-3 and a thermal conductivity in the range of approximately 1-10 W/cmK.
42. A structure as recited in claim 31 ,
wherein said first surface is bonded in direct contact with said third surface at about room temperature without application of pressure during bonding with a bond strength sufficient to permit at least one of grinding and polishing of said second surface after bonding said first and third surfaces.
43. A structure as recited in claims 1 , wherein said first oxide layer is nonadhesively directly bonded to said second oxide layers.
44. A structure as recited in claim 18 , wherein said first bonding layer is nonadhesively directly bonded to said second bonding layer.
45. A structure as recited in claim 31 , wherein said first surface is nonadhesively bonded in direct contact with said third surface.