Patent Assignment
Reel/Frame 043029/0657
Change of Name
Recorded: 2017-06-28
Pages: 6
Assignor
ZIPTRONIX , INC.
Executed: 2017-05-26
Assignee
INVENSAS BONDING TECHNOLOGIES, INC.
3025 ORCHARD PARKWAY, SAN JOSE, CALIFORNIA, 95134
Covered Properties
(83)
Self Aligned Symmetric Process and Device
Patent:
6,368,930 →
Application:
09/165,203 →
Self- Aligned Symmetric Intrinsic Device
Patent:
6,242,794 →
Application:
09/311,149 →
Three Dimensional Device Intergration Method and Integrated Device
Patent:
6,984,571 →
Application:
09/410,054 →
Method for Low Temperature Bonding and Bonded Structure
Patent:
6,902,987 →
Application:
09/505,283 →
Three Dimensional Device Integration Method and Integrated Device
Patent:
6,500,694 →
Application:
09/532,886 →
Method of Epitaxial-Like Wafer Bonding at Low Temperature and Bonded Structure
Patent:
6,563,133 →
Application:
09/635,272 →
Self Aligned Symmetric Intrinsic Process and Device
Three Dimensional Device Integration Method and Integrated Device
Three Dimensional Device Intergration Method and Intergrated Device
Self Aligned Symmetric Intrinsic Process and Device
Three Dimensional Device Integration Method and Integrated Device
Three Dimensional Device Integration Method and Integrated Device
Wafer Bonding Hermetic Encapsulation
Three Dimensional Device Integration Method and Integrated Device
Method of Epitaxial-Like Wafer Bonding at Low Temperature and Bonded Structure
Method for Room Temperature Metal Direct Bonding
Method of Room Temperature Covalent Bonding
Method for Low Temperature Bonding and Bonded Structure
Single Mask via Method and Device
Patent:
6,867,073 →
Application:
10/688,910 →
Method for Low Temperature Bonding and Bonded Structure
Wafer Scale Die Handling
Method for Low Temperature Bonding and Bonded Structure
Wafer Bonding Hermetic Encapsulation
Single Mask via Method and Device
Room Temperature Metal Direct Bonding
Method of Detachable Direct Bonding at Low Temperatures
3D Ic Method and Device
Method of Room Temperature Covalent Bonding
Room Temperature Metal Direct Bonding
Method for Low Temperature Bonding and Bonded Structure
Method for Low Temperature Bonding and Bonded Structure
Method of Room Temperature Covalent Bonding
Single Mask via Method and Device
3D Ic Method and Device
Method for Low Temperature Bonding and Bonded Structure
Method for Low Temperature Bonding and Bonded Structure
Room Temperature Metal Direct Bonding
Method for Low Temperature Bonding and Bonded Structure
Method of Room Temperature Covalent Bonding
Method of Room Temperature Covalent Bonding
Heterogeneous Annealing Method and Device
3D Ic Method and Device
Room Temperature Metal Direct Bonding
Heterogeneous Annealing Method and Device
Method for Low Temperature Bonding and Bonded Structure
3D Ic Method and Device
Room Temperature Metal Direct Bonding
Method of Room Temperature Covalent Bonding
Three Dimensional Device Integration Method and Integrated Device
Method for Low Temperature Bonding and Bonded Structure
3D Ic Method and Device
Conductive Barrier Direct Hybrid Bonding
Heterogeneous Annealing Method and Device
Method for Low Temperature Bonding and Bonded Structure
Room Temperature Metal Direct Bonding
Increased Contact Alignment Tolerance for Direct Bonding
Application:
62/269,412 →
Die Stacking with Direct Bonds
Application:
62/278,354 →
Systems and Methods for Efficient Die Transfer
Application:
62/303,930 →
Three Dimensional Device Integration Method and Integrated Device
Stacked Dies and Methods for Forming Bonded Structures
Method for Low Temperature Bonding and Bonded Structure
Semiconductor Interface Structures and Methods for Forming Same
Application:
62/402,913 →
Native Inter-Die Interconnect
Application:
62/405,833 →
Increased Contact Alignment Tolerance for Direct Bonding
Three Dimensional Device Integration Method and Integrated Device
Bonded Structures
Systems and Methods for Efficient Transfer of Semiconductor Elements
Die tray with channel
Application:
62/438,223 →
Processed Substrate
Application:
62/439,746 →
Microelectronic assembly from processed substrate
Application:
62/439,762 →
Processing Stacked Substrates
Application:
62/439,771 →
Bonded Structures with Integrated Passive Component
Application:
62/440,161 →
Structure with Integrated Metallic Waveguide
Bonded Structures with Integrated Passive Component
Application:
15/426,942 →
Publication:
US US20180190583A1
Bonded Structures
Application:
62/457,116 →
Bonded Structures
Application:
62/458,441 →
Multi-metal contact structures
Application:
62/472,877 →
Seal for microelectronic assembly
Application:
62/474,478 →
Broadside Resonator Coupler
Application:
62/480,022 →
Die Processing
Application:
62/488,340 →
Probe methodology for ultrafine pitch Interconnects
Application:
62/504,792 →
Processed stacked dies
Application:
62/504,834 →
Wafer level capacitors
Application:
62/518,472 →
Related Assignments
(8)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Dec 20, 2004
From: TONG, QIN-YI; ENQUIST, PAUL M.; SCOT ROSE, ANTHONY
To: ZIPTRONIX, INC.
Reel/Frame 016092/0716 →
Assignment of Assignor's Interest
May 2, 2006
From: TONG, QIN-YI
To: ZIPTRONIX, INC.
Reel/Frame 017848/0533 →
Assignment of Assignor's Interest
Aug 17, 2015
From: ENQUIST, PAUL M.; FOUNTAIN, GAIUS GILLMAN, JR.
To: ZIPTRONIX, INC.
Reel/Frame 036355/0287 →
Security Interest
Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
Security Interest
Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
Release of Security Interest
Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION
Reel/Frame 052920/0001 →
Change of Name
Aug 14, 2023
From: INVENSAS BONDING TECHNOLOGIES, INC.
To: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
Reel/Frame 064586/0880 →
Assignment of Assignor's Interest
Oct 21, 2025
From: ENQUIST, PAUL M.; FOUNTAIN, GAIUS GILLMAN, JR.; TONG, QIN-YI
To: ZIPTRONIX, INC.
Reel/Frame 072622/0084 →