Three dimensional device integration method and integrated device
View Patent ↗A method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.
1. A bonding method comprising:
depositing a first layer on a first semiconductor element;
polishing the first layer;
depositing a second layer on the polished first layer of the first semiconductor element;
polishing the second layer;
providing a second semiconductor element having a third layer provided thereon;
bringing into direct contact the polished second layer of the first semiconductor element with the third layer of the second semiconductor element; and
directly bonding the second polished layer of the first semiconductor element to the third layer of the second semiconductor element.
2. The method of claim 1 , wherein depositing the first layer comprises depositing silicon dioxide and depositing the second layer comprises depositing silicon dioxide.
3. The method of claim 1 , wherein the first layer has a thermal conductivity in a range of 1 W/cmK to 10 W/cmK.
4. The method of claim 1 , wherein polishing the second layer comprises polishing an upper surface of the second layer to have a surface roughness in a range of 5 Å to 15 Å.
5. The method of claim 1 , wherein polishing the second layer comprises polishing an upper surface of the second layer to have a surface roughness less than or equal to 5 Å.
6. The method of claim 1 , further comprising depositing a fourth layer on the polished second layer of the first semiconductor element and polishing the fourth layer.
7. The method of claim 1 , further comprising depositing a fifth layer on the third layer of the second semiconductor element.
8. The method of claim 1 , wherein the directly bonding comprises bonding without application of sustained pressure.
9. The method of claim 1 , wherein the directly bonding comprises nonadhesive bonding.
10. The method of claim 1 , wherein the directly bonding comprises bonding at room temperature.
11. A bonding method comprising:
depositing a first oxide layer on a first semiconductor element;
depositing a second oxide layer on the first oxide layer of the first semiconductor element;
providing a second semiconductor element;
bringing into direct contact the second oxide layer of the first semiconductor element with the second semiconductor element; and
directly bonding the second oxide layer of the first semiconductor element to the second semiconductor element.
12. The method of claim 11 , further comprising polishing the first oxide layer before depositing the second oxide layer.
13. The method of claim 11 , further comprising polishing the second oxide layer before the bringing into direct contact.
14. The method of claim 13 , wherein the polishing the second oxide layer comprises polishing the upper surface of the second oxide layer to have a surface roughness in a range of 5 Å to 10 Å.
15. The method of claim 13 , further comprising depositing a third oxide layer on the polished second oxide layer of the first semiconductor element and polishing the third oxide layer.
16. The method of claim 11 , wherein the first oxide layer has a thermal conductivity in a range of 1 W/cmK to 10 W/cmK.
17. The method of claim 11 , wherein the directly bonding comprises bonding without application of sustained pressure.
18. The method of claim 11 , wherein the directly bonding comprises nonadhesive bonding.
19. The method of claim 11 , further comprising depositing a third oxide layer on the second semiconductor element and polishing the third oxide layer.