IP Library Granted Patent US 7,526,595
Granted Patent B2
US 7,526,595 · App. 10/202,722 · Granted Apr 28, 2009

Data path master/slave data processing device apparatus and method

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Quick Facts
Patent No.
US 7,526,595
App. No.
10/202,722
Granted
Apr 28, 2009
Kind
B2
Abstract

An apparatus and method is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data processor core, and a functionally coupled data processor slave. Both the data processing master and the data processing slave are coupled to a common bus or common crossbar switch. The data processing device processes the data associated with transfers to or from the data processor slave. System masters will direct transactions that require data processing to the data processing slave, which will indirectly interact with the target memory slave. System masters will direct transactions that do not require data processing, directly to the target memory slave.

Claims (19)

1. A method for writing to a memory slave on a target bus, comprising:

initiating a write, the write requiring data processing, by a system master coupled to a first bus, the first bus coupled to an arbiter;

receiving data from the system master by a data processing slave coupled to a second bus, the second bus coupled to the arbiter, wherein the data processing slave receives only data to be processed from the system master and transmits processed data to the system master wherein the data to be processed and the processed data is passed through the arbiter;

transmitting by the data processing slave data to a data processing core;

processing by the data processing core of the data;

transmitting by the data processing core processed data to a data processing master coupled to the first bus; and

transmitting by the data processing master processed data to the memory slave, wherein the data processing master receives only data to be processed from the memory slave and transmits processed data to the memory slave, wherein the data to be processed and the processed data is passed through the arbiter.

2. A method for reading from a memory slave on a target bus, comprising:

initiating a read of data, the data requiring data processing, by a system master coupled to a first bus, the first bus coupled to an arbiter;

requesting a disengagement of the system master by a data processing slave coupled to a second bus, the second bus coupled to the arbiter;

recognizing a read sequence as requiring data processing and additional data to be retrieved by a data processing master coupled to the first bus;

capturing the data to be processed from a memory slave coupled to the second bus by a data processing master, wherein the data processing master captures only data to be processed from the memory slave and transmits processed data to the memory slave, wherein the data to be processed and the processed data is passed through the arbiter;

transferring data from the data processing master to a data processing core;

processing by the data processing core the data;

transmitting by the data processing core processed data to the data processing slave;

data holding by the data processing slave, for a period until the system master repeats the original request for data; and

returning by the data processing slave processed data to the system master, wherein the data processing slave captures only data to be processed from the system master and transmits processed data to the system master, wherein the data to be processed and the processed data is passed through the arbiter.

3. The method of claim 2 , further comprising the step of transmitting processed data to the system master from the data processing slave.

4. The method of claim 2 , further comprising the step of the data processing slave monitoring for a re-request from the system master.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2013
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: INTEL CORPORATION
Reel/Frame 030228/0415 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2002
From: DRERUP, BERNARD CHARLES; SIEGMUND, JR., RICHARD; WOLFORD, BARRY JOE
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 013154/0856 →