Patent Assignment
Reel/Frame 030228/0415
Assignment of Assignor's Interest
Recorded: 2013-04-16
Pages: 13
Assignor
INTERNATIONAL BUSINESS MACHINES CORPORATION
Executed: 2013-04-08
Assignee
INTEL CORPORATION
2200 MISSION COLLEGE BOULEVARD, SANTA CLARA, CALIFORNIA, 95054
Covered Properties
(102)
Microprocessor with Pipeline Synchronization
Patent:
6,052,771 →
Application:
09/008,792 →
Programmable Hardware Event Monitoring Method
Patent:
6,134,676 →
Application:
09/070,145 →
Selective Routing of Data in a Multi-Level Memory Architecture Based on Source Identification Information
Patent:
6,314,500 →
Application:
09/228,314 →
System and Method for Power Optimization in Parallel Units
Patent:
6,289,465 →
Application:
09/228,884 →
Instruction Cache for Multithreaded Processor
Patent:
6,161,166 →
Application:
09/266,133 →
Layered Local Cache with Imprecise Reload Mechanism
Patent:
6,434,667 →
Application:
09/340,075 →
Layered Local Cache Mechanism with Split Register Load Bus and Cache Load Bus
Patent:
6,405,285 →
Application:
09/340,076 →
Transfer of Data Between Processors in a Multi-Processor System
Patent:
6,484,220 →
Application:
09/383,736 →
Method and Apparatus for Implementing Execution Predicates in a Computer Processing System
Patent:
6,513,109 →
Application:
09/387,220 →
Method and Apparatus for Allocating Data and Instructions Within a Shared Cache
Patent:
6,532,520 →
Application:
09/394,965 →
Method, System, and Program for Managing Requests to a Cache Using Flags to Queue and Dequeue Data in a Buffer
Patent:
6,438,651 →
Application:
09/432,044 →
Circuits, Systems and Methods for Performing Branch Predictions by Selectively Accessing Bimodal and Fetch-Based History Tables
Patent:
6,976,157 →
Application:
09/435,070 →
System and Method for Prefetching Data to Multiple Levels of Cache Including Selectively Using a Software Hint to Override a Hardware Prefetch Mechanism
Patent:
6,460,115 →
Application:
09/435,865 →
Tlb Parity Error Recovery
Patent:
6,901,540 →
Application:
09/435,868 →
Method, Apparatus, and Computer Program Product for Controlling Data Transfer
Patent:
6,684,279 →
Application:
09/436,202 →
Method and Apparatus to Eliminate Failed Snoops of Transactions Caused by Bus Timing Conflicts in a Distributed Symmetric Multiprocessor System
Patent:
6,529,990 →
Application:
09/436,203 →
Cache Coherency Protocol in Which a Load Instruction Hint Bit Is Employed to Indicate Deallocation of a Modified Cache Line Supplied by Intervention
Patent:
6,374,333 →
Application:
09/437,176 →
Cache Cohererency Protocol Employing a Read Operation Including Programmable Flag to Indicate Deallocation of an Intervened Cache Line
Patent:
6,345,342 →
Application:
09/437,177 →
Multiprocessor System Bus Protocol Including Read Request Having Flag Indicating Deallocation Upon Sourcing a Requested Modified Value
Patent:
6,345,343 →
Application:
09/437,178 →
High Performance Multiprocessor System with Modified-Unsolicited Cache State
Patent:
6,321,306 →
Application:
09/437,179 →
Cache Coherency Protocol That Provides a Flag from an Intervening Cache to Indicate Deallocation of a Modified Cache Line
Patent:
6,349,369 →
Application:
09/437,180 →
Cache Allocation Mechanism for Modified Unsolicited Cache State That Modifies Victimization Priority Bits
Patent:
6,345,344 →
Application:
09/437,181 →
Prefetching Using Future Branch Path Information Derived from Branch Prediction*
Patent:
7,441,110 →
Application:
09/458,883 →
Microprocessor with Primary and Secondary Issue Queue
Patent:
6,609,190 →
Application:
09/478,311 →
System and Method for Dynamically Allocating Computer Memory Based on Block Size
Patent:
6,643,754 →
Application:
09/504,610 →
Composite Uniprocessor
Patent:
6,766,437 →
Application:
09/514,630 →
Network Processor Which Makes Thread Execution Control Decisions Based on Latency Event Lengths
Patent:
7,093,109 →
Application:
09/542,189 →
Controller for Multiple Instruction Thread Processors
Patent:
6,931,641 →
Application:
09/542,206 →
Dual Master Device for Improved Utilization of a Processor Local Bus
Patent:
6,654,836 →
Application:
09/597,769 →
Processor and Method of Executing Load Instructions Out-of-Order Having Reduced Hazard Penalty
Patent:
6,868,491 →
Application:
09/598,434 →
Processor and Method Having a Load Reorder Queue That Supports Reservations
Patent:
6,725,358 →
Application:
09/598,435 →
Branch Target Cache and Method for Efficiently Obtaining Target Path Instructions for Tight Program Loops
Patent:
6,829,702 →
Application:
09/626,247 →
Method for Implementing a Variable-Partitioned Queue for Simultaneous Multithreaded Processors
Patent:
6,931,639 →
Application:
09/645,081 →
Employing a Data Mover to Communicate Between Dynamically Selected Zones of a Central Processing Complex
Prefetching Instructions in Mis-Predicted Path for Low Confidence Branches
System and Method for Power Optimization in Parallel Units
Multi-Master Computer System with Overlapped Read and Write Operations and Scalable Address Pipelining
Compression of Execution Path History to Improve Branch Prediction Accuracy
Universal Load Address/Value Prediction Using Stride-Based Pattern History and Last-Value Prediction in a Two-Level Table Scheme
Multithreaded Processor Efficiency by Prefetching Instructions for a Scheduled Thread
Symmetric Multiprocessor Coherence Mechanism
Simd Datapath Coupled to Scalar/Vector/Address/Conditional Data Register File with Selective Subpath Scalar Processing Mode
Method and Apparatus for Aligning Memory Write Data in a Microprocessor
Partitioned Cache of Multiple Logical Levels with Adaptive Reconfiguration Based on Multiple Criteria
Multi-Level Classification Method for Transaction Address Conflicts for Ensuring Efficient Ordering in a Two-Level Snoopy Cache Architeture
Method and Apparatus for Fault-Tolerance via Dual Thread Crosschecking
Critical Datapath Error Handling in a Multiprocessor Architecture
Method and Apparatus for Managing Low Power Processor States
Method for Sharing a Translation Lookaside Buffer Between Cpus
Data Path Master/Slave Data Processing Device Apparatus and Method
Reducing Latency of a Snoop Tenure
System and Method for Persistent and Robust Storage Allocation
Re-Ordering a First Request Within a Fifo Request Queue to a Different Queue Position When the First Request Receives a Retry Response from the Target
System and Method for Implementing an Adaptive Replacement Cache Policy
On-Chip Data Transfer in Multi-Processor System
Sender to Receiver Request Retry Method and Apparatus
DMA prefetch
Application:
10/401,411 →
Publication:
US 2004/0193754
Virtualization of a Global Interrupt Queue
Method, Apparatus and Computer Program Product for Dynamically Minimizing Translation Lookaside Buffer Entries Across Contiguous Memory
Effects of Prefetching on I/O Requests in an Information Processing System
System and Method for Providing Processor Recovery in a Multi-Core System
Memory Management in Multiprocessor System
Cacheable Dma
System and Method for Grouping Processors and Assigning Shared Memory Space to a Group in Heterogeneous Computer Environment
System and Method for Sharing Memory by Heterogen Ous Processors
Autonomic Method and Apparatus for Local Program Code Reorganization Using Branch Count Per Instruction Hardware
Autonomic Method and Apparatus for Counting Branch Instructions to Generate Branch Statistics Meant to Improve Branch Predictions
Method for Supporting Improved Burst Transfers on a Coherent Bus
Reducing Power Consumption in a Logically Partitioned Data Processing System with Operating System Call That Indicates a Selected Processor Is Unneeded for a Period of Time
Controller for Multiple Instruction Thread Processors
System and Method for Persistent and Robust Storage Allocation
Load Lookahead Prefetch for Microprocessors
Dma Prefetch
Snoop Filtering System in a Multiprocessor System
Method and Apparatus for Filtering Snoop Requests Using Stream Registers
Method and Apparatus for Filtering Snoop Requests in a Point-to-Point Interconnect Architecture
Novel Snoop Filter for Filtering Snoop Requests
System and Method for Adaptively Managing Pages in a Memory
Placing a Processor into a Gradual Slow Mode of Operation in Response to a Detected Livelock Condition Within a Processor Pipeline
Issue Unit for Placing a Processor into a Gradual Slow Mode of Operation in Response to a Detected Livelock Condition Within a Processor Pipeline
Local and Global Branch Prediction Information Storage
Livelock Resolution Method
Virtualization of a Global Interrupt Queue
System and Method for Sharing Memory by Heterogeneous Processors
System and Method for Persistent and Robust Storage Allocation
Reducing Power Consumption in a Logically Partitioned Data Processing System
Load Lookahead Prefetch for Microprocessors
Method and Apparatus for Filtering Snoop Requests in a Point-to-Point Interconnect Architecture
Grouping Processors and Assigning Shared Memory Space to a Group in a Heterogeneous Computer Environment
Novel Snoop Filter for Filtering Snoop Requests
Snoop Filtering System in a Multiprocessor System
Design Structure for a Livelock Resolution Circuit
Method and Apparatus for Filtering Snoop Requests Using Stream Registers
Processor Livelock Recovery by Gradual Stalling of Instruction Processing Rate During Detection of Livelock Condition
Issue Unit for Placing a Processor into a Gradual Slow Mode of Operation
Data Path Master/Slave Data Processing Device Apparatus
Local and Global Branch Prediction Information Storage
Livelock Resolution
Data Path Master/Slave Data Processing Device
Application:
12/719,683 →
Publication:
US 2010/0169527
Novel Snoop Filter for Filtering Snoop Requests
Scalable address pipelining on busses of computer systems
Application:
60/213,040 →
Fault-tolerance via dual thread crosschecking
Application:
60/272,138 →