System and method for sharing memory by heterogeneous processors
View Patent ↗A system for sharing memory by heterogeneous processors, each of which is adapted to process its own instruction set, is presented. A common bus is used to couple the common memory to the various processors. In one embodiment, a cache for more than one of the processors is stored in the shared memory. In another embodiment, some of the processors include a local memory area that is mapped to the shared memory pool. In yet another embodiment, local memory included on one or more of the processors is partially shared so that some of the local memory is mapped to the shared memory area, while remaining memory in the local memory is private to the particular processor.
1. A method for sharing a memory between a plurality of heterogeneous processors, said method comprising:
receiving a memory request;
allocating a first memory partition on the shared memory that corresponds to the memory request, the first memory partition accessible by one or more first processors that are adapted to process a first instruction set;
assigning a second memory partition on the shared memory to one or more second processors that are adapted to process a second instruction set, wherein the first processors and the second processors are heterogeneous;
wherein the shared memory is partitioned into a non-private memory area that is accessible by one or more of the first processors and one or more of the second processors;
wherein one of the second processors is adapted to access a private memory area that is not accessible by any of the first processors;
managing the first memory partition and the second memory partition using a common memory map;
wherein the common memory map includes a plurality of regions, wherein at least one of the regions is selected from the group consisting of an external system memory region, a local storage aliases region, a TLB region, an MFC region, an operating system region, and an I/O devices region; and
wherein the TLB region includes cross-references between virtual addresses and real addresses, the common memory map and the cross-references shared between the first processors and the second processors.
2. The method as described in claim 1 wherein one of the first processors includes an operating system whereby the first processor controls the common memory map.
3. The method as described in claim 1 wherein at least one of the first processors is a Power PC and wherein at least one of the second processors is included in a synergistic processing unit.
4. The method as described in claim 3 wherein the shared memory corresponds to the synergistic processing unit.
5. The method as described in claim 1 wherein at least one of the second processors uses a direct memory access controller for accessing the shared memory.