System and method for providing processor recovery in a multi-core system

1. A multiprocessor system for detecting and recovering from errors, the multiprocessor system comprising:

a first processor;

a second processor;

said first processor detecting a local error internal to the first processor and initiating a recovery process, said first processor and said second processor synchronizing at least one recovery action during said recovery process;

said error is a recoverable error;

said first processor executing a first reset phase;

said second processor executing said first reset phase;

said first processor and second processor executing a second reset phase synchronization;

said second processor halting further instruction decoding and allowing in-flight instructions to complete and checkpoint;

said second processor sends a stores released signal to said first processor to indicate completion of allowing in-flight instructions to complete and checkpoint;

said first processor delaying executing said second reset phase until receiving said stores released signal.

2. The multiprocessor system of claim 1 wherein:

said first processor sends said second processor an array reset signal upon completing said second reset phase;

said second processor sends said first processor said array reset signal upon completing said second reset phase;

said first processor and said second processor performing a first pass of register refresh in synchronization in response to said array reset signals.

3. The multiprocessor system of claim 1 wherein:

said error is a non-recoverable error;

said first processor executing a checkstop routine upon detection of said non-recoverable error, said first processor sending a checkstop error signal to aid second processor;

said second processor executing a delayed checkstop sequence to enter a stable sparing state.

4. The multiprocessor system of claim 3 wherein:

said delayed checkstop sequence includes said second processor executing instructions until a sparing bit indicates that sparing is allowed.

5. The multiprocessor system of claim 4 wherein:

said delayed checkstop sequence includes initiating a pipe drain by allowing in-process instructions to checkpoint.

6. The multiprocessor system of claim 5 wherein:

said delayed checkstop sequence includes releasing stores queued up by previously checkpointed instructions.

7. The multiprocessor system of claim 6 wherein:

said second processor sends a checkstop error signal to said first processor upon completing said delayed checkstop sequence;

said first processor and said second processor entering a checkstop mode in synchronization.

8. The multiprocessor system of claim 1 wherein:

said first processor and said second processor arc located on one physical chip.

9. The multiprocessor system of claim 1 wherein:

said first processor and maid second processor sham common resources, including cache storage.

10. A processor for detecting and recovering from errors in a multiprocessor system, the processor implementing a recovery process comprising:

detecting local error internal to a first processor and initiating a recovery process, notifying a second processor of said error;

postponing recovery processing until receiving a synchronization signal from said second processor;

said error is a recoverable error;

said processor executing a first reset phase;

said first processor delaying executing of a second reset phase until receiving a stores released signal from said second processor, the stores releases signal indicating that the second processor has halted further instruction decoding and allowed in-flight instructions to complete and checkpoint.

11. The processor of claim 10 wherein:

said processor performs a first pass of register refresh in response to receiving an array reset signal from said second processor.

12. The processor of claim 10 wherein:

said error Is a non-recoverable error;

said processor executing a check stop routine upon detection of said non-recoverable error,

said processor sending a checkstop error signal to said second processor.

13. The processor of claim 12 wherein:

said first processor receives a checkstop error signal from said second processor enters a checkstop mode.