IP Library Granted Patent US 7,143,246
Granted Patent B2
US 7,143,246 · App. 10/759,939 · Granted Nov 28, 2006

Method for supporting improved burst transfers on a coherent bus

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Quick Facts
Patent No.
US 7,143,246
App. No.
10/759,939
Granted
Nov 28, 2006
Kind
B2
Abstract

In a multiprocessor system, comprising master and slave processors, a cache coherency controller, and address concentration devices; a method for improving coherent data transfers is described. A command transaction is generated, and a subsequent command from an initiator. Tags added to the responses or further request responses, stream on high-speed busses. Snoops and accumulated snoops expand on cacheline requests as each processor separates burst commands into multiple cacheline requests. Address concentrators containing a cacheline queue function, funnel transaction requests to a global serialization device, where a queuing process prioritizes indicia and coordinates the results among the processors. The cache issues a single burst command for each affected line. System coherency, performance, and latency improvements occur. Additional support for burst transfers between coherent processors is provided.

Claims (47)

1. A method in a multiprocessor system, including at least two processors and a cache coherency controller, coupled to address concentration devices, the method operable in said cache coherency controller for improving coherent data transfers, the method comprising the steps of:

initiating a first memory transaction request command to a first processor of said multiple processors;

determining priority receipt status of a next memory transaction request;

expanding snoop responses and accumulated snoop responses to provide a coherency action for all cacheline requests utilizing a burst command;

forwarding said transaction requests from said master or said controller to a solitary global serialization device, said serialization device further comprising a multiple cacheline request indicator;

grouping multiple and sequential coherent transfers into a burst operation on said processor bus;

determining occurrence of the burst operation;

timing said burst operation;

snooping said burst operation to form a plurality of snoop replies;

concentrating all addresses of said plurality of snoop replies to form a combined snoop response; and

broadcasting the combined snoop response to a plurality of device entities.

2. The method of claim 1 wherein said determining said occurrence of said burst operation comprises detecting an indication that a plurality of cachelines is requested.

3. The method of claim 2 wherein each processor of said at least two processors supports snooping a plurality of cachelines for the burst operation.

4. The method of claim 1 wherein said snooping said burst operation comprises separating said burst operation into multiple cacheline requests on a bus.

5. The method of claim 1 wherein said snooping said burst operation comprises at least a bus and at least a cache directly supporting a burst operation.

6. The method of claim 1 wherein broadcast of said combined snoop response is between pluralities of processors.

7. The method of claim 1 wherein said determining said occurrence of said burst operation includes the step of:

determining whether a previous cacheline request corresponding to said processor is already present in a first-in first-out queue; and

queuing said cacheline request in response to a determination that said cacheline request is not already present in said first-in first-out queue.

8. The method of claim 1 wherein accumulated snoop responses agglomerate as a combined response only on notification of individual responses of said entities within said processors.

9. A method of performing a burst transfer on a bus with cache coherency, the method comprising:

initiating a burst transfer command on a bus connecting a plurality of processors, wherein the burst transfer command is a request to access a block of data that comprises two or more cachelines;

performing, by each given processor within the plurality of processors, a cache snoop of the burst transfer command to form a burst snoop response;

accumulating burst snoop responses for the two or more cachelines from the plurality of processors to form a combined snoop response; and

broadcasting the combined snoop response to the plurality of processors,

wherein performing a cache snoop of the burst transfer command comprises:

splitting, by a snooping processor within the plurality of processors, the burst transfer command into a plurality of single cacheline requests;

forwarding the plurality of single cacheline requests to a plurality of entities within the snooping processor; and

performing, by each entity within the snooping processor, a cache snoop of each of the plurality of single cacheline requests to form a plurality of single cacheline snoop responses.

10. The method of claim 9 , wherein initiating a burst transfer command comprises:

responsive to a plurality of transfer commands requesting to access a plurality of sequential cachelines from a plurality of entities within an initiating processor, accumulating the plurality of transfer commands to form the burst transfer command.

11. The method of claim 10 , further comprising:

responsive to receipt of the combined snoop response at the initiating processor, separating the combined snoop response into a plurality of individual snoop responses; and

forwarding the plurality of individual snoop responses to the pluralities of entities within the initiating processor.

12. The method of claim 9 , wherein performing a cache snoop of the burst transfer command further comprises:

returning the plurality of single cacheline snoop responses from each entity within the snooping processor to a gathering function within the snooping processor, wherein the gathering function accumulates the plurality of single cacheline snoop responses to form a burst snoop response for the snooping processor.

13. A data processing system comprising:

a plurality of processors; and

a bus connecting the plurality of processors,

wherein an initiating processor from the plurality of processors initiates a burst transfer command on the bus and wherein the burst transfer command is a request to access a block of data that comprises two or more cachelines;

wherein each given processor within the plurality of processors performs a cache snoop of the burst transfer command to form a burst snoop response;

wherein a snoop response gathering function accumulates burst snoop responses for the two or more cachelines from the plurality of processors to form a combined snoop response and broadcasts the combined snoop response to the plurality of processors,

wherein a separation function within a snooping processor within the plurality of processors splits the burst transfer command into a plurality of single cacheline requests and forwards the plurality of single cacheline requests to a plurality of entities within the snooping processor; and

wherein each entity within the snooping processor performs a cache snoop of each of the plurality of single cacheline requests to form a plurality of single cacheline snoop responses.

14. The data processing system of claim 13 , wherein, responsive to a plurality of transfer commands requesting to access a plurality of sequential cachelines from a plurality of entities within the initiating processor, a gathering function within the initiating processor accumulates the plurality of transfer commands to form the burst transfer command.

15. The data processing system of claim 14 , wherein, responsive to receipt of the combined snoop response at the initiating processor, a separation function within the initiating processor separates the combined snoop response into a plurality of individual snoop responses and forwards the plurality of individual snoop responses to the pluralities of entities within the initiating processor.

16. The data processing system of claim 13 , wherein a gathering function within the snooping processor accumulates the plurality of single cacheline snoop responses to form a burst snoop response for the snooping processor.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2013
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: INTEL CORPORATION
Reel/Frame 030228/0415 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 16, 2004
From: JOHNS, CHARLES RAY
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 014911/0942 →