Method and device for dynamic interrupt target selection
View Patent ↗A method and device for dynamically targeting interrupts in a computer system. When an operation is initiated, an identifier for the initiator of the operation is stored along with an operation identifier. When an operation completes or needs processor attention due to an error condition or otherwise, the processor or node to interrupt is determined based on the stored indication of the initiator of the operation. An interrupt target data structure may be provided that contains associations between sources that initiate operations and those targets that can service interrupts. If a target scheduled to field an interrupt becomes unavailable, the interrupt can be retargeted to another processor or node by reloading an entry in the interrupt target data structure.
1. A method for retargeting interrupts in a computer system, the method comprising:
providing an interrupt target data structure which includes a plurality of entries, wherein each entry includes a source identifier and a target identifier of a plurality of target identifiers, said target identifier identifying one of a plurality of target resources;
in response to detecting a first target resource of the plurality of target resources is unavailable:
examining each entry of the target data structure; and
replacing each instance of a first target identifier in the target data structure with a target identifier that is different from the first target identifier, in response to determining the first target identifier corresponds to the unavailable first target resource.
2. A method according to claim 1 wherein a first entry of the plurality of entries includes a first source identifier and a second target identifier, the method further comprising:
associating a first operation with the first source identifier and the first entry;
accessing the first entry at the completion of the first operation to retrieve the second target identifier;
interrupting a processor that corresponds to the second target identifier;
associating a second operation with the first source identifier and the first entry;
detecting the processor corresponding to the second target identifier is unavailable;
replacing the second target identifier in the first entry with a third target identifier;
accessing the first entry at the completion of the second operation to retrieve the third target identifier; and
interrupting a processor which corresponds to the third target identifier.
3. A method according to claim 1 further including:
initiating an operation and associating the source identifier with the operation; and
using the source identifier associated with the operation to access an entry in the interrupt target data structure to determine a target processor to interrupt, when the operation completes.
4. A method according to claim 1 , wherein the source identifier for each entry specifies at least a given source node and a given processor within the node.
5. A method according to claim 1 , wherein the source identifier for each entry specifies at least a given source node.
6. A device for interrupting a target processor in a computer system at the completion of an operation initiated by a given source processor within a given source node, the device comprising:
an interrupt target data structure, the data structure including a plurality of entries, each entry including a source identifier and a target identifier of a plurality of target identifiers, said target identifier identifying one of a plurality of target resources;
logic configured to respond to detecting a first target resource of the plurality of target resources is unavailable by:
examining each entry of the target data structure; and
replacing each instance of a first target identifier in the target data structure with a target identifier that is different from the first target identifier, in response to determining the first target identifier corresponds to the unavailable first target resource.
7. A device according to claim 6 wherein a first entry of the plurality of entries includes a first source identifier and a second target identifier, the device further comprising logic configured to:
associate a first operation with the first source identifier and the first entry;
access the first entry at the completion of the first operation to retrieve the second target identifier;
interrupt a processor that corresponds to the second target identifier;
associate a second operation with the first source identifier and the first entry;
detect the processor corresponding to the second target identifier is unavailable;
replace the second target identifier in the first entry with a third target identifier;
access the first entry at the completion of the second operation to retrieve the third target identifier; and
interrupt a processor which corresponds to the third target identifier.
8. A device according to claim 6 further including:
logic for initiating an operation and associating the source identifier with the operation; and
logic for using the source identifier associated with the operation to access an entry in the interrupt target data structure to determine a processor to interrupt, when the operation completes.
9. A device according to claim 6 , wherein the source identifier for each entry specifies at least a given source node and a given processor within the source node.
10. A device for interrupting a target processor in a computer system at the completion of an operation initiated by a given source processor within a given source node, the device comprising:
means for associating each of a plurality of source identifiers with a target identifier of a plurality of target identifiers, each of said target identifiers identifying one of a plurality of target resources;
means for detecting a target resource of the plurality of target resources is unavailable;
means for examining each of the associations of source identifiers and target identifiers and replacing in the means for associating each instance of a first target identifier with a target identifier that is different from the first target identifier, in response to determining the first target identifier corresponds to the unavailable first target resource.
11. A device according to claim 10 wherein a first source identifier is associated with a second target identifier, the device further including:
means for associating a first operation with the first source identifier;
means for retrieving the second target identifier at the completion of the first operation and interrupting a processor that corresponds to the second target identifier;
means for associating a second operation with the first source identifier;
means for detecting the processor corresponding to the second target identifier is unavailable;
means for replacing the second target identifier with a third target identifier;
means for retrieving the third target identifier at the completion of the second operation and interrupting a processor that corresponds to the third target identifier.
12. A device according to claim 10 further including:
means for initiating an operation and associating the source identifier with the operation; and
means for using the source identifier associated with the operation to access a target identifier to determine a processor to interrupt, when the operation completes.
13. A device according to claim 10 , wherein each source identifier specifies at least a given source node and a given processor within the source node.
14. A method according to claim 1 , wherein the target identifier for each entry specifies at least a given target node.
15. A method according to claim 14 , wherein the target identifier further specifies a processor within a given target node.
16. A device according to claim 6 , wherein the target identifier specifies at least a given target node.
17. A device according to claim 16 , wherein the target identifier further specifies a processor within a given target node.