Patent Assignment
Reel/Frame 037280/0232
Merger and Change of Name
Recorded: 2015-12-14
Pages: 11
Assignors
ORACLE USA, INC.
Executed: 2010-02-12
SUN MICROSYSTEMS, INC.
Executed: 2010-02-12
ORACLE AMERICA, INC.
Executed: 2010-02-12
Assignee
ORACLE AMERICA, INC.
500 ORACLE PARKWAY, REDWOOD SHORES, CALIFORNIA, 94065
Covered Properties
(100)
Platform Independent on-Line Project Management Tool
Graphics System with Just-in-Time Decompression of Compressed Graphics Data
Patent:
7,071,935 →
Application:
09/332,919 →
Methods and Apparatus for Providing a Virtual Host in Electronic Messaging Servers
Patent:
7,058,683 →
Application:
09/521,282 →
Replacing an Email Attachment with an Address Specifying Where the Attachment Is Stored
Patent:
7,054,905 →
Application:
09/539,269 →
Method and Apparatus for a Pipelined Network
Patent:
7,065,580 →
Application:
09/540,731 →
Data Network with Independent Transmission Channels
Patent:
7,061,929 →
Application:
09/540,779 →
Method and System for Pro-Active Credential Refreshing
Patent:
7,058,798 →
Application:
09/547,183 →
Elimination of End-Around-Carry Critical Path in Floating Point Add/Subtract Execution Unit
Patent:
7,054,898 →
Application:
09/632,235 →
Messaging System Using Pairs of Message Gates in a Distributed Computing Environment
Patent:
7,065,574 →
Application:
09/658,805 →
Efficient Construction of Message Endpoints
Patent:
7,072,967 →
Application:
09/660,562 →
Methods and Apparatus for Accessing Synchronized Broadcast Data
Patent:
7,062,779 →
Application:
09/724,732 →
Scalable Routing Scheme for a Multi-Path Interconnection Fabric
Using Messaging to Manage Scene-Based Rendering
Method and Apparatus for Facilitating Instant Failover During Packet Routing
Identifying References to Objects During Bytecode Verification
Storage Array Employing Scrubbing Operations Using Multiple Levels of Checksums
Flushable Free Register List Having Selected Pointers Moving in Unison
Method for Keystroke Delivery to Descendants of Inactive Windows
Methods and System for Efficient Association Traversals
Client Aware Extensible Markup Language Content Retrieval and Integration in a Wireless Portal System
Frameworks for Generation of Java Macro Instructions for Instantiating Java Objects
Methods, Systems, and Articles of Manufacture for Implementing a Runtime Logging Service Storage Infrastructure
Method and Apparatus for Managing Data Imaging in a Distributed Computer System
Http Transaction Monitor with Capacity to Replay in Debugging Session
Method and Apparatus for Remote Software Code Update
Dynamic Object Usage Pattern Learning and Efficient Caching
Methods and Systems for Developing Data Flow Programs
Method and Apparatus for Removing Class Initialization Barriers from Shared Compiled Methods
Application Programming Interface for Connecting a Platform Independent Plug-in to a Web Browser
Floating Point System with Improved Support of Interval Arithmetic
Floating Point Unit for Detecting and Representing Inexact Computations Without Flags or Traps
Method and Apparatus for Solving an Inequality Constrained Global Optimization Problem
Determining Object Graph and Object Graph Projection
System Using Peer Discovery and Peer Membership Protocols for Accessing Peer-to-Peer Platform Resources on a Network
Dirty Data Protection for Cache Memories
Ibist Identification Loopback Scheme
Reducing the Memory Footprint of Applications Executed in a Virtual Machine
Out-Of-Order Processor That Reduces Mis-Speculation Using a Replay Scoreboard
Abstract User Interface Manager with Prioritization
Callback Event Listener Mechanism for Resource Adapter Work Executions Performed by an Application Server Thread
System and Method for Controlling Multiple Devices via General Purpose Input/Output (Gpio) Hardware
Software Controllable Register Map
System and Method of Using Extensions in a Data Structure Without Interfering with Applications Unaware of the Extensions
Rules-Based Configuration Problem Detection
Method for Debugging an Integrated Circuit
Method and Apparatus for Providing Error Correction Within a Register File of a Cpu
Input/Output Device Having Linearized Output Response
System and Method for Rapid Fault Isolation in a Storage Area Network
System and Method for Interfacing Computer System Information Protocol Interface Modules
Updating High Speed Parallel I/O Interfaces Based on Counters
Synchronizing Video Formats with Dissimilar Timing
Method and System for a Portable Adaptable Operating Environment Identity
Method and Device for Dynamic Interrupt Target Selection
Multiprocessor Systems
Method and Apparatus for Restricted Run-Time Environment with Dynamic User Context
Method and Apparatus for Metrics Approval Mechanism
Clock Distribution Architecture Having Clock and Power Failure Protection
Methods and Systems for Software Watchdog Support
Extending Custom Application Development Environment Modules to a Second Application Development Environment
System and Method for Assessing Compatibility Risk
Generic Interface and Framework to Publish and Monitor Platform Configuration
Defect Tracking by Utilizing Real-Time Counters in Network Computing Environments
Method and Apparatus for Initializing Romized System Classes at Virtual Machine Build Time
Method and Apparatus for Isolating Faulty Semiconductor Devices in a Multiple Stream Graphics System
Dynamically Configurable Unit Conversion Mechanism
System Prom Integrity Checker
Efficiently Supporting the Existence of Long Trains in a Generation Managed by the Train Algorithm
Timely Finalization of System Resources
Patent:
7,069,279 →
Application:
10/287,858 →
A System for Controlling a Tunable Delay by Transfering a Signal from a First Plurality of Points Along a First Propagating Circuit to a Second Plurality of Points Along a Second Propagating Circuit
Better Placement of Objects Reachable from Outside a Generation Managed by the Train Algorithm
Collection-Tick Mechanism for a Collector Based on the Train Algorithm
System and Method for Evaluating and Executing Hierarchies of Rules
Method and System for Reporting Standardized and Verified Data
Scalable, Space-Efficient, Parallel Remembered-Sets
I/O Resonance Cancellation Circuit Based on Charge-Pumped Capacitors
Versioning and Replaying Performance Tuning Projects
Clock Edge Value Calculation in Hardware Simulation
Method and Apparatus for Generating and Verifying Libraries for Atpg Tool
Embedded Integrated Circuit Aging Sensor System
Concurrently Programmable Dynamic Memory Built-in Self-Test (Bist)
Parallel Card Table Scanning and Updating
Efficient Collocation of Evacuated Objects in a Copying Garbage Collector Using Variably Filled Local Allocation Buffers
Incremental Scanning of Enormous Objects to Improve Scheduling and Pause-Time Behavior of Garbage Collection
Supporting Interactions Between Different Versions of Software for Accessing Remote Objects
Modeling Overlapping of Memory References in a Queueing System Model
Clock Skew Reduction Technique Based on Distributed Process Monitors
Computer System, Method, and Program Product for Performing a Data Access from Low-Level Code
Remembered-Set Scrubbing to Remove Stale Entries in an Incremental Garbage Collector
Optimized Cache Structure for Multi-Texturing
Stream Based Memory Manager with Function Specific Hardware Logic for Accessing Data as a Stream in Memory
Computer System Including a Memory Controller Configured to Perform Pre-Fetch Operations
Distributed Infiniband Verification Protocol
Method for Handling Condition Code Modifiers in an Out-of-Order Multi-Issue Multi-Stranded Processor
Patent:
7,065,635 →
Application:
10/738,576 →
Method and Apparatus for Detection and Isolation During Large Scale Circuit Verification
Patent:
7,051,303 →
Application:
10/747,577 →
Dynamic Memory Throttling for Power and Thermal Limitations
Patent:
7,064,994 →
Application:
10/768,782 →
Scan Chain Verification Using Symbolic Simulation
Patent:
7,055,118 →
Application:
10/790,650 →
Delay Estimation Using Edge Specific Miller Capacitances
Patent:
7,051,305 →
Application:
10/832,760 →
Arbiters with Preferential Enables for Asynchronous Circuits
Patent:
7,064,583 →
Application:
10/922,744 →
Method and Apparatus for Using Capacitively Coupled Communication Within Stacks of Laminated Chips
Algorithm for Full-Chip Resistance Extraction
Patent:
7,069,527 →
Application:
11/212,513 →
Related Assignments
(4)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Aug 13, 2001
From: CHATTERJEE, AMLAN; JAIN, DIVYA; MUELLER, THOMAS; TRAN, LUU
To: SUN MICROSYSTEMS, INC.
Reel/Frame 012098/0992 →
Assignment of Assignor's Interest
Oct 19, 2007
From: LEE, WHAY S.
To: SUN MICROSYSTEMS, INC.
Reel/Frame 020009/0802 →
Corrective Assignment to Correct the Recordation Date of 10/19/2007 to 1/04/2001. Previously Recorded on Reel 002009 Frame 0802. Assignor(S) Hereby Confirms the Assignment.
Dec 4, 2007
From: LEE, WHAY S.
To: SUN MICROSYSTEMS, INC.
Reel/Frame 020192/0877 →
Merger and Change of Name
Dec 16, 2015
From: ORACLE USA, INC.; SUN MICROSYSTEMS, INC.; ORACLE AMERICA, INC.
To: ORACLE AMERICA, INC.
Reel/Frame 037302/0633 →