Algorithm for full-chip resistance extraction
View Patent ↗A method to convert a wire layout geometry to a filament topology for determination of chip resistance is provided. The method includes resolving overlap of layout segments of the wire layout geometry and inserting a vertical filament into each of the layout segments. The method further includes connecting vertical filaments using lateral connections and merging connected parallel filaments. The method also includes removing open filaments and modifying the filament structure in a bend region based on relative dimensions of the vertical filaments within the bend region.
1. A method to convert a wire layout geometry to a filament topology for determination of chip resistance, comprising:
resolving overlap of layout segments of the wire layout geometry;
inserting a vertical filament into each of the layout segments;
connecting vertical filaments using lateral connections;
merging connected parallel filaments;
removing open filaments; and
modifying a filament structure in a bend region based on relative dimensions of the vertical filaments within the bend region.
2. A method to convert a wire layout geometry to a filament topology for determination of chip resistance as recited claim 1 , wherein resolving the overlap of layout segments includes eliminating overlaps of the segments.
3. A method to convert a wire layout geometry to a filament topology for determination of chip resistance as recited claim 1 , wherein inserting the vertical filament into each of the layout segments includes adding the vertical filament in a midpoint location between a first node of the segment and a second node of the segment.
4. A method to convert a wire layout geometry to a filament topology for determination of chip resistance as recited claim 1 , wherein connecting vertical filaments using lateral connections includes one of:
connecting a vertical filament and an open node, or
connecting a vertical filament and another vertical filament.
5. A method to convert a wire layout geometry to a filament topology for determination of chip resistance as recited claim 1 , wherein merging parallel filaments includes merging parallel filaments which are touching at a juncture between the parallel filaments.
6. A method to convert a wire layout geometry to a filament topology for determination of chip resistance as recited claim 1 , wherein merging parallel filaments includes designating a merged filament as a juncture between the parallel filaments.
7. A method to convert a wire layout geometry to a filament topology for determination of chip resistance as recited claim 1 , wherein modifying the filament structure in the bend region based on relative dimensions of the vertical filaments within the bend region includes generating a step filament structure in the bend region when a width of a first vertical filament is less than a half of a height of an adjacent vertical filament and when a width of a second vertical filament less than a half of the height of the adjacent vertical filament.
8. A method to convert a wire layout geometry to a filament topology for determination of chip resistance as recited claim 1 , wherein modifying the filament structure in the bend region based on relative dimensions of the vertical filaments within the bend region includes generating a floating filament structure in the bend region when a width of a first vertical filament is greater than twice a height of an adjacent vertical filament or when a width of a second vertical filament is greater than twice the height of the adjacent vertical filament.
9. A computer readable media having program instructions to convert a wire layout geometry to a filament topology for determination of chip resistance, the computer readable media comprising:
program instructions for resolving overlap of layout segments;
program instructions for inserting a vertical filament into each of the layout segments;
program instructions for connecting vertical filaments using lateral connections;
program instructions for merging connected parallel filaments;
program instructions for removing open filaments; and
program instructions for modifying a filament structure in a bend region based on relative dimensions of vertical filaments within the bend region.
10. A computer readable media as recited in claim 9 , wherein the program instructions for resolving the overlap of layout segments include program instructions for eliminating overlaps of the segments.
11. A computer readable media as recited in claim 9 , wherein program instructions for inserting the vertical filament into each of the layout segments includes adding vertical filaments in a midpoint location between a first node of the segment and a second node of the segment.
12. A computer readable media as recited in claim 9 , wherein program instructions for connecting vertical filaments with lateral connections includes:
program instructions for connecting a vertical filament with an open node, and
program instructions for connecting a vertical filament with another vertical filament.
13. A computer readable media as recited in claim 9 , wherein program instructions for merging parallel filaments includes program instructions for merging parallel filaments which are touching at a juncture between the parallel filaments.
14. A computer readable media as recited in claim 9 , wherein program instructions for merging parallel filaments includes program instructions for designating a merged filament as a juncture between the parallel filaments.
15. A computer readable media as recited in claim 9 , wherein program instructions for modifying the filament structure in the bend region based on relative dimensions of the vertical filaments within the bend region includes program instructions for generating a step filament structure in the bend region when a width of a first vertical filament is less than a half of a height of an adjacent vertical filament and when a width of a second vertical filament less than a half of the height of the adjacent vertical filament.
16. A computer readable media as recited in claim 9 , wherein program instructions for modifying the filament structure in the bend region based on relative dimensions of the vertical filaments within the bend region includes program instructions for generating a floating filament structure in the bend region when a width of a first vertical filament is greater than twice a height of an adjacent vertical filament or when a width of a second vertical filament is greater than twice the height of the adjacent vertical filament.
17. A method to convert a wire layout geometry to a filament topology for determination of chip resistance, comprising:
resolving overlap of layout segments;
inserting a vertical filament into each of the layout segments;
connecting vertical filaments using lateral connections;
merging connected parallel filaments;
removing open filaments; and
modifying a filament structure within a bend region including generating a particular filament structure in the bend region, the particular filament structure corresponding to particular dimensional ratios of the vertical filaments within the bend region.
18. A method to convert a wire layout geometry to a filament topology for determination of chip resistance as recited claim 17 , wherein resolving the overlap of layout segments include eliminating overlaps of the segments.
19. A method to convert a wire layout geometry to a filament topology for determination of chip resistance as recited claim 17 , wherein inserting vertical filaments into the layout segments includes adding vertical filaments in a midpoint location between a first node of the segment and a second node of the segment.
20. A method to convert a wire layout geometry to a filament topology for determination of chip resistance as recited claim 17 , wherein connecting vertical filaments with lateral connections includes one of:
connecting a vertical filament with an open node, or
connecting a vertical filament with another vertical filament.
21. A method to convert a wire layout geometry to a filament topology for determination of chip resistance as recited claim 17 , wherein merging parallel filaments includes merging parallel filaments which are touching at a juncture between the parallel filaments.
22. A method to convert a wire layout geometry to a filament topology for determination of chip resistance as recited claim 17 , wherein merging parallel filaments includes designating a merged filament as a juncture between the parallel filaments.
23. A method to convert a wire layout geometry to a filament topology for determination of chip resistance as recited claim 17 , wherein generating the particular filament structure in the bend region includes generating a step filament structure in the bend region when a width of a first vertical filament is less than a half of a height of an adjacent vertical filament and when a width of a second vertical filament less than a half of the height of the adjacent vertical filament.
24. A method to convert a wire layout geometry to a filament topology for determination of chip resistance as recited claim 17 , wherein generating the particular filament structure in the bend region includes generating a floating filament structure in the bend region when a width of a first vertical filament is greater than twice a height of an adjacent vertical filament or when a width of a second vertical filament is greater than twice the height of the adjacent vertical filament.