Clock skew reduction technique based on distributed process monitors

1. An apparatus, comprising:

a plurality of oscillators distributed across the apparatus, wherein at least one of the plurality of oscillators has a frequency dependent on a characteristic of the apparatus;

a first tunable buffer arranged to propagate a first clock signal;

a processor arranged to output at least one control signal dependent on the frequency; and

a first bias generator arranged to adjust a propagation delay through the first tunable buffer dependent on the at least one control signal, wherein a propagation delay through at least one other tunable buffer is not dependent on the at least one control signal.

2. The apparatus of claim 1 , further comprising a counter, wherein the counter is arranged to count a number of clock cycles generated by at least one of the plurality of oscillators, and wherein the counter is operatively connected to the processor.

3. The apparatus of claim 1 , wherein the characteristic of the apparatus is selected from at least one of a temperature, a voltage, and a process.

4. The apparatus of claim 1 , wherein the first tunable buffer is arranged within a clock tree.

5. The apparatus of claim 1 , wherein the plurality of oscillators are arranged in a grid pattern.

6. The apparatus of claim 1 , wherein the at least one of the plurality of oscillators is located on a hot spot.

7. The apparatus of claim 1 , wherein at least one of the plurality of oscillators comprises a ring oscillator.

8. The apparatus of claim 1 , wherein the first bias generator comprises a plurality of transistors arranged to adjust a bias voltage, and wherein a delay through the first tunable buffer is dependent on the bias voltage.

9. The apparatus of claim 1 , wherein the first tunable buffer comprises a device that control a rate of transition of a propagation of the first clock signal.

10. The apparatus of claim 1 , further comprising:

a second tunable buffer arranged to propagate a second clock signal; and

a second bias generator arranged to adjust a propagation delay through the second tunable buffer, wherein the second bias generator is adjustable dependent on the frequency.

11. The apparatus of claim 10 , wherein the second tunable buffer is arranged within a clock tree.

12. A method, comprising:

generating a plurality of oscillator signals at a plurality of locations on an integrated circuit, wherein a frequency of at least one of the plurality of oscillator signals is dependent on a characteristic of the integrated circuit;

monitoring the at least one of the plurality of the oscillator signals;

determining an adjustment of a propagation delay through a first tunable buffer dependent on the monitoring;

generating at least one control signal dependent on the determining; and

adjusting the propagation delay through the first tunable buffer dependent on the at least one control signal, wherein a propagation delay through at least one other tunable buffer is not dependent on the at least one control signal.

13. The method of claim 12 , wherein the monitoring comprises:

counting a number of clock cycles of the at least one of the plurality of oscillator signals, wherein the determining is dependent on the counting.

14. The method of claim 12 , wherein the characteristic of the integrated circuit is selected from at least one of a temperature, a voltage, and a process.

15. The method of claim 12 , further comprising:

inputting a clock signal at an input of the first tunable buffer; and

distributing the clock signal from the first tunable buffer across the integrated circuit.

16. The method of claim 12 , wherein the at least one of the plurality of oscillator signals is dependent on a hot spot of the integrated circuit.

17. The method of claim 12 , wherein the generating comprises using a ring oscillator.

18. The method of claim 12 , wherein the adjusting comprises generating a bias voltage, wherein the propagation delay through the first tunable buffer is dependent on the bias voltage.

19. The method of claim 12 , further comprising:

determining an adjustment of a propagation delay through a second tunable buffer dependent on the monitoring; and

adjusting the propagation delay through the second tunable buffer dependent on the determining.

determining an adjustment of a second tunable buffer dependent on the monitoring; and

adjusting the second tunable buffer dependent on the determining.