Clock edge value calculation in hardware simulation

1. A method for providing a next clock edge value calculation, comprising:

obtaining a clock file data, wherein the clock file data comprises a clock label, a rise value, a fall value, and a period value;

calculating a next clock edge value using the clock file data, wherein calculating the next clock edge value comprises:

determining a first delta value and a second delta value using the rise value, the fall value, and the period value, and

alternately adding the first delta value and the second delta value to a previous clock edge value; and

generating an output file using the next clock edge value.

2. The method of claim 1 , further comprising:

creating the clock file data during compilation of a circuit design.

3. The method of claim 1 , further comprising:

debugging a circuit design using the output file.

4. The method of claim 1 , further comprising:

tracing a value at each clock edge using the output file.

5. The method of claim 4 , wherein the output file comprises a post-simulation analysis file.

6. The method of claim 1 , further comprising:

comparing the output file to a golden file.

7. The method of claim 1 , wherein the clock file data comprises at least one selected from a group consisting of a periodic clock, a plurality of periodic clocks, and a plurality of periodic clocks and non-periodic clocks.

8. The method of claim 1 , wherein calculating the next clock edge value comprises calculating the next clock edge value based on a type of clock information contained in clock file data.

9. A method for providing an nth clock edge value calculation, comprising:

obtaining a clock file data and an n value, wherein the clock file data comprises a clock label, a rise value, a fall value, and a period value;

calculating an nth clock edge value using the clock file data and the n value, wherein calculating the nth clock edge value comprises:

calculating the nth clock edge value using the rise value and the period value, if the n value is even, and

calculating the nth clock edge value using the fall value and the period value, if the n value is odd; and

generating an output file using the nth clock edge value.

10. The method of claim 9 , further comprising:

creating the clock file data during compilation of a circuit design.

11. The method of claim 9 , further comprising:

using the output file to perform at least one selected from a group consisting of debugging a circuit design and tracing a value at each clock edge.

12. The method of claim 11 , wherein the output file comprises a post-simulation analysis file.

13. The method of claim 9 , further comprising:

comparing the output file to a golden file.

14. The method of claim 9 , wherein the clock file data comprises at least one selected from a group consisting of a periodic clock, a plurality of periodic clocks, and a plurality of periodic clocks and non-periodic clocks.

15. The method of claim 9 , wherein calculating the nth clock edge value comprises calculating the nth clock edge value based on a type of clock information contained in clock file data.

16. A method for providing a clock edge value calculation, comprising:

obtaining a clock file data and an n value, wherein the clock file data comprises a clock label, a rise value, a fall value, and a period value;

calculating a next clock edge value using the clock file data,

wherein calculating the next clock edge value comprises:

determining a first delta value and a second delta value using the rise value, the fall value, and the period value, and

alternately adding the first delta value and the second delta value to a previous clock edge value;

calculating an nth clock edge value using the clock file data and the n value,

wherein calculating the nth clock edge value comprises:

calculating the nth clock edge value using the rise value and the period value, if the n value is even, and

calculating the nth clock edge value using the fall value and the period value, if the n value is odd; and

generating an output file using the next clock edge value and the nth clock edge value.

17. The method of claim 16 , further comprising:

creating the clock file data during compilation of a circuit design.

18. The method of claim 16 , further comprising:

using the output file to perform at least one selected from a group consisting of debugging a circuit design and tracing a value at each clock edge.

19. The method of claim 18 , wherein the output file comprises a post-simulation analysis file.

20. The method of claim 16 , further comprising:

comparing the output file to a golden file.

21. The method of claim 16 , wherein the clock file data comprises at least one selected from a group consisting of a periodic clock, a plurality of periodic clocks, and a plurality of periodic clocks and non-periodic clocks.

22. A computer system for debugging a circuit design, comprising:

a host computer operatively connected to a simulation hardware;

a simulation control program executing on the host computer receiving a clock file data for the circuit design; and

a data store storing an output file generated by:

obtaining the clock file data, wherein the clock file data comprises a clock label, a rise value, a fall value, and a period value; and

calculating a next clock edge value using the clock file data,

wherein calculating the next clock edge value comprises:

determining a first delta value and a second delta value using the rise value, the fall value, and the period value; and

alternately adding the first delta value and the second delta value to a previous clock edge value.

23. The computer system of claim 22 , further comprising: a test interface allowing debugging the circuit design using the output file.

24. The computer system of claim 22 , wherein the clock file data is created during compilation of a circuit design.

25. The computer system of claim 22 , wherein the clock file data comprises at least one selected from a group consisting of a periodic clock, a plurality of periodic clocks, and a plurality of periodic clocks and non-periodic clocks.

26. A computer system for debugging a circuit design, comprising:

a host computer operatively connected to a simulation hardware;

a simulation control program executing on the host computer receiving a clock file data for the circuit design; and

a data store storing an output file generated by:

obtaining the clock file data and an n value, wherein the clock file data comprises a clock label, a rise value, a fall value, and a period value; and

calculating an nth clock edge value using the clock file data and the n value,

wherein calculating the nth clock edge value comprises:

calculating the nth clock edge value using the rise value and the period value, if the n value is even, and

calculating the nth clock edge value using the fall value and the period value, if the n value is odd.

27. The computer system of claim 26 , further comprising:

a test interface allowing debugging the circuit design using the output file.

28. The computer system of claim 26 , wherein the clock file data is created during compilation of the circuit design.

29. The computer system of claim 26 , wherein the clock file data comprises at least one selected from a group consisting of a periodic clock, a plurality of periodic clocks, and a plurality of periodic clocks and non-periodic clocks.

30. An apparatus for providing a next clock edge value calculation, comprising:

means for obtaining a clock file data, wherein the clock file data comprises a clock label, a rise value, a fall value, and a period value;

means for calculating a next clock edge value using the clock file data,

wherein calculating the next clock edge value comprises:

determining a first delta value and a second delta value using the rise value, the fall value, and the period value, and

alternately adding the first delta value and the second delta value to a previous clock edge value; and

means for generating an output file using the next clock edge value.

31. An apparatus for providing an nth clock edge value calculation, comprising:

means for obtaining a clock file data and an n value, wherein the clock file data comprises a clock label, a rise value, a fall value, and a period value;

means for calculating an nth clock edge value using the clock file data and the n value,

wherein calculating the nth clock edge value comprises:

calculating the nth clock edge value using the rise value and the period value, if the n value is even, and

calculating the nth clock edge value using the fall value and the period value, if the n value is odd; and

means for generating an output file using the nth clock edge value.