IP Library Granted Patent US 6,928,527
Granted Patent B2
US 6,928,527 · App. 10/211,234 · Granted Aug 9, 2005

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Quick Facts
Patent No.
US 6,928,527
App. No.
10/211,234
Granted
Aug 9, 2005
Kind
B2
Abstract

A method for operating a memory device, the method comprising marking a portion of a memory device associated with a group of bits comprising at least one bit upon which an operation is to be performed, and operating on the group of bits and skipping operating on at least one unmarked portion of the memory device in an operation cycle of the memory device. A random access memory (RAM) device is also disclosed comprising a plurality of addresses for storing therein data, and at least one address pointer for at least one of the addresses in the RAM device.

Claims (17)

1. A method for operating a memory device, the method comprising:

marking a portion of a memory device that comprises data associated with performance of an operation on a memory cell, wherein said memory device is a random access memory (RAM) device, said RAM device comprising a plurality of addresses for storing therein data; and wherein said marking further comprises:

finding a first address by providing at least one address pointer for each of said addresses in said RAM device, said at least one address pointer comprising bits, and marking the bits of said at least one address pointer; and

proceeding to a second address and marking the at least one address pointer that corresponds to said second address with an identifier that identifies said first address; and

retrieving said data from said portion that is marked, and skipping retrieving data from at least one unmarked portion of said memory device in an operation cycle of said memory device.

2. The method according to claim 1 and further comprising retrieving data only from those addresses that have marked address pointers.

3. The method according to claim 2 and further comprising:

finding a first address that comprises data for operating on said memory cell; and

proceeding to a second address and marking at least one address pointer, referred to as a verification pointer, which corresponds to said second address, with an identifier that identifies said first address.

4. The method according to claim 3 wherein said marking said verification pointer comprises providing said memory device with at least two address pointers for each of said addresses in said RAM device, wherein one of said address pointers is dedicated for indicating from which addresses data is to be retrieved, and another of said address pointers comprises said verification pointer.

5. The method according to claim 4 and further comprising retrieving data only from those addresses that have marked verification pointers.

6. A memory device comprising:

a random access memory (RAM) device comprising a plurality of addresses for storing therein data, and at least one address pointer for at least one of said addresses in said RAM device;

a controller to mark bits in said at least one address pointer, wherein said controller is adapted to scan said RAM device address by address.

7. The memory device according to claim 6 , wherein said RAM device communicates with an array comprising programmable bits, wherein said RAM device comprises a Boolean operation performable on binary integers 0 and 1 that designate a programmed state of a bit in said array (referred to as “ARRAY”) and whether said RAM device includes programming instructions for said bit (referred to as “RAMs”), wherein binary integer 0 indicates that said bit is programmed, and binary integer 1 indicates that said bit is not programmed.

8. The memory device according to claim 7 wherein said Boolean operation comprises a “complex mode” function comprising the Boolean operation (“RAM”) OR (NOT “ARRAY”).

9. The memory device according to claim 7 wherein said Boolean operation comprises an “n-complex mode” function comprising the Boolean operation (“RAM”) AND (“ARRAY”).

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE FOLLOWING NUMBERS 6272046,7277824,7282374,7286384,7299106,7337032,7460920,7519447 PREVIOUSLY RECORDED ON REEL 039676 FRAME 0237. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Oct 16, 2018
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MORGAN STANLEY SENIOR FUNDING
Reel/Frame 047797/0854 →
SECURITY INTEREST Recorded Aug 15, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039676/0237 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 14, 2010
From: INFINEON TECHNOLOGIES FLASH LTD.
To: QIMONDA AG
Reel/Frame 023778/0339 →
CHANGE OF NAME Recorded Aug 18, 2003
From: INGENTIX LTD.
To: INFINEON TECHNOLOGIES FLASH LTD.
Reel/Frame 014390/0773 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 4, 2002
From: COHEN, ZEEV; DVIR, RAN; MAAYAN, EDUARDO
To: SAIFUN SEMICONDUCTORS LTD.; INGENTIX LTD.
Reel/Frame 013458/0479 →