Patent Assignment
Reel/Frame 035623/0001
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2015-05-08
Received: 2015-05-08
Pages: 181
Assignor
QIMONDA AG
Executed: 2014-10-09
Assignee
INFINEON TECHNOLOGIES AG
AM CAMPEON 1-12, NEUBIBERG, DEX, 85579, GERMANY
Covered Applications
(100)
APPARATUS, SYSTEM AND METHOD FOR MERGING CODE LAYERS FOR AUDIO ENCODING AND DECODING AND ERROR CORRECTION THEREOF
App. No. 14/685,984
→
ORGAN ARREST, PROTECTION, PRESERVATION AND RECOVERY
App. No. 14/633,932
→
CONTINUOUSLY INTERLEAVED ERROR CORRECTION
App. No. 14/526,148
→
NETWORK DISTRIBUTED PACKET-BASED SYNCHRONIZATION
App. No. 14/503,082
→
PROGRAM GUIDE SYSTEM WITH MONITORING OF ADVERTISEMENT USAGE AND USER ACTIVITIES
App. No. 14/252,760
→
TIMING SYNCHRONIZATION FOR NETWORKS WITH RADIO LINKS
App. No. 14/160,449
→
PARALLEL CRC COMPUTATION WITH DATA ENABLES
App. No. 14/135,437
→
DELAY MEASUREMENT IN A POINT TO MULTIPOINT SYSTEM
App. No. 14/040,320
→
Memory Read-Out
App. No. 13/941,372
→
SEMICONDUCTOR MEMORY HAVING NON-STANDARD FORM FACTOR
App. No. 13/926,226
→
PHYSICAL LAYER PROCESSING OF TIMESTAMPS AND MAC SECURITY
App. No. 13/671,480
→
WAN TRANSPORT OF FRAMES WITH MAC SECURITY
App. No. 13/671,516
→
HEAT TRANSFER SYSTEM
App. No. 13/568,968
→
CIRCUIT
App. No. 13/443,011
→
CONCENTRIC PHASE CHANGE MEMORY ELEMENT
App. No. 13/364,727
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MEMORY DEVICES INCLUDING SEMICONDUCTOR PILLARS
App. No. 13/360,965
→
MEMORY-MODULE CONTROLLER, MEMORY CONTROLLER AND CORRESPONDING MEMORY ARRANGEMENT, AND ALSO METHOD FOR ERROR CORRECTION
App. No. 13/287,488
→
INTEGRATED CIRCUIT HAVING A SEMICONDUCTOR SUBSTRATE WITH BARRIER LAYER
App. No. 13/151,408
→
INTEGRATED DEVICE
App. No. 13/050,645
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METHOD OF APPLYING AN ADHESIVE LAYER ON THINCUT SEMICONDUCTOR CHIPS OF A SEMICONDUCTOR WAFER
App. No. 11/720,954
→
INTEGRATED CIRCUIT HAVING A MATERIAL STRUCTURED BY A PROJECTION
App. No. 12/975,891
→
MEMORY USING TUNNELING FIELD EFFECT TRANSISTORS
App. No. 12/975,997
→
INTEGRATED CIRCUIT AND PROGRAMMABLE DELAY
App. No. 12/939,468
→
TIMESTAMP PREDICTOR FOR PACKETS OVER A SYNCHRONOUS PROTOCOL
App. No. 12/895,467
→
SYSTEM AND METHOD FOR SIGNAL ADJUSTMENT
App. No. 12/886,791
→
METHOD FOR FABRICATING AN INTEGRATED CIRCUIT INCLUDING RESISTIVITY CHANGING MATERIAL HAVING A PLANARIZED SURFACE
App. No. 12/856,007
→
APPARATUS AND METHOD FOR MANUFACTURING A MULTIPLE-CHIP MEMORY DEVICE WITH MULTI-STAGE TESTING
App. No. 12/856,225
→
Memory Including Vertical Bipolar Select Device and Resistive Memory Element
App. No. 12/853,791
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MEMORY DEVICE INCLUDING AN ELECTRODE HAVING AN OUTER PORTION WITH GREATER RESISTIVITY
App. No. 12/826,201
→
SEMICONDUCTOR MEMORY MODULE, ELECTRONIC APPARATUS AND METHOD FOR OPERATING THEREOF
App. No. 12/759,827
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CURRENT CONSTRICTING PHASE CHANGE MEMORY ELEMENT STRUCTURE
App. No. 12/727,672
→
SEMICONDUCTOR MEMORY WITH MEMORY CELL PORTIONS HAVING DIFFERENT ACCESS SPEEDS
App. No. 12/710,800
→
SEMICONDUCTOR MEMORY HAVING NON-STANDARD FORM FACTOR
App. No. 12/693,837
→
RESISTIVE MEMORY CELL ACCESSED USING TWO BIT LINES
App. No. 12/692,044
→
DATA EXCHANGE IN RESISTANCE CHANGING MEMORY FOR IMPROVED ENDURANCE
App. No. 12/687,951
→
PHOTOVOLTAIC DEVICE
App. No. 12/638,674
→
SEMICONDUCTOR DEVICE WITH PLASTIC PACKAGE MOLDING COMPOUND, SEMICONDUCTOR CHIP AND LEADFRAME AND METHOD FOR PRODUCING THE SAME
App. No. 10/577,173
→
CHIP ARRANGEMENT AND METHOD OF MANUFACTURING A CHIP ARRANGEMENT
App. No. 12/485,727
→
INTEGRATED CIRCUIT COMPRISING CONDUCTIVE LINES AND CONTACT STRUCTURES AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT
App. No. 12/354,140
→
ELECTRICAL CIRCUIT WITH A NANOSTRUCTURE AND METHOD FOR PRODUCING A CONTACT CONNECTION OF A NANOSTRUCTURE
App. No. 11/577,070
→
INTEGRATED CIRCUIT, METHOD TO PROGRAM A MEMORY CELL ARRAY OF AN INTEGRATED CIRCUIT, AND MEMORY MODULE
App. No. 12/351,023
→
INTEGRATED CIRCUIT COMPRISING A THYRISTOR AND METHOD OF CONTROLLING A MEMORY CELL COMPRISING A THYRISTOR
App. No. 12/339,722
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DISTRIBUTED COMMAND AND ADDRESS BUS ARCHITECTURE FOR A MEMORY MODULE HAVING PORTIONS OF BUS LINES SEPARATELY DISPOSED
App. No. 12/328,690
→
DIGITALLY CONTROLLED CML BUFFER
App. No. 12/275,372
→
METHOD AND APPARATUS TO REDUCE POWER CONSUMPTION BY TRANSFERRING FUNCTIONALITY FROM MEMORY COMPONENTS TO A MEMORY INTERFACE
App. No. 12/273,348
→
INTEGRATED CIRCUIT WITH STACKED DEVICES
App. No. 12/271,313
→
METHOD FOR PRODUCING AN INTEGRATED CIRCUIT AND ARRANGEMENT COMPRISING A SUBSTRATE
App. No. 12/269,612
→
CONTROL CIRCUIT IN A MEMORY CHIP
App. No. 12/262,124
→
METHOD AND APPARATUS FOR PERFORMING INTERNAL HIDDEN REFRESHES WHILE LATCHING READ/WRITE COMMANDS, ADDRESS AND DATA INFORMATION FOR LATER OPERATION
App. No. 12/255,755
→
4 F2 MEMORY CELL ARRAY
App. No. 12/252,826
→
MEMORY CELL ARRAY COMPRISING WIGGLED BIT LINES
App. No. 12/252,853
→
INTERCONNECT STRUCTURES AND METHODS
App. No. 12/252,236
→
INTEGRATED CIRCUIT WITH A CONTACT STRUCTURE INCLUDING A PORTION ARRANGED IN A CAVITY OF A SEMICONDUCTOR STRUCTURE
App. No. 12/251,864
→
PACKAGING SYSTEMS AND METHODS
App. No. 12/252,244
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INTEGRATED CIRCUIT WITH CONTROL CIRCUIT FOR PERFORMING RETENTION TEST
App. No. 12/251,010
→
INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES
App. No. 12/249,060
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INTEGRATED CIRCUIT WITH SWITCHING UNIT FOR MEMORY CELL COUPLING, AND METHOD FOR PRODUCING AN INTEGRATED CIRCUIT FOR MEMORY CELL COUPLING
App. No. 12/248,505
→
MEMORY DEVICE AND MEMORY SYSTEM COMPRISING A MEMORY DEVICE AND A MEMORY CONTROL DEVICE
App. No. 12/248,759
→
INTEGRATED CIRCUIT
App. No. 12/247,763
→
INTEGRATED CIRCUIT INCLUDING A HETERO-INTERFACE AND SELF ADJUSTED DIFFUSION METHOD FOR MANUFACTURING THE SAME
App. No. 12/242,137
→
METHOD OF MANUFACTURING INTEGRATED CIRCUITS INCLUDING A FET WITH A GATE SPACER AND A FIN
App. No. 12/242,039
→
INTEGRATED CIRCUIT WITH A RECTIFIER ELEMENT
App. No. 12/241,992
→
MEMORY DEVICE REFRESH METHOD AND APPARATUS
App. No. 12/240,331
→
APPARATUS FOR THE DYNAMIC DETECTION, SELECTION AND DESELECTION OF LEAKING DECOUPLING CAPACITORS
App. No. 12/239,624
→
MULTI-PORT DRAM ARCHITECTURE FOR ACCESSING DIFFERENT MEMORY PARTITIONS
App. No. 12/235,396
→
METHOD AND SYSTEM INCLUDING PLURAL MEMORY CONTROLLERS AND A MEMORY ACCESS CONTROL BUS FOR ACCESSING A MEMORY DEVICE
App. No. 12/235,063
→
MEMORY DIES FOR FLEXIBLE USE AND METHOD FOR CONFIGURING MEMORY DIES
App. No. 12/234,312
→
INTEGRATED CIRCUIT
App. No. 12/234,398
→
SYSTEM AND METHOD FOR PACKAGED MEMORY
App. No. 12/212,400
→
HORIZONTAL DUAL IN-LINE MEMORY MODULES
App. No. 12/209,019
→
PHASE CHANGE MEMORY CELL WITH MOSFET DRIVEN BIPOLAR ACCESS DEVICE
App. No. 12/207,229
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INTEGRATED CIRCUIT INCLUDING DOPED SEMICONDUCTOR LINE HAVING CONDUCTIVE CLADDING
App. No. 12/206,439
→
INTEGRATED CIRCUIT WITH MEMORY HAVING A CURRENT LIMITING SWITCH
App. No. 12/206,378
→
Memory scheduler for managing maintenance operations in a resistive memory in response to a trigger condition
App. No. 12/202,581
→
MULTI-MODE BUS INVERSION METHOD AND APPARATUS
App. No. 12/202,485
→
HEAT TRANSFER SYSTEM FOR MEMORY MODULES
App. No. 12/201,524
→
MEMORY DEVICE HAVING AN EVALUATION CIRCUIT
App. No. 12/201,192
→
DIGITAL DATA INVERSION FLAG GENERATOR CIRCUIT
App. No. 12/201,876
→
METHOD AND APPARATUS FOR REDUCING CHARGE TRAPPING IN HIGH-K DIELECTRIC MATERIAL
App. No. 12/201,223
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MEMORY DEVICE WITH MULTIPLE CAPACITOR TYPES
App. No. 12/200,041
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CONCENTRIC PHASE CHANGE MEMORY ELEMENT
App. No. 12/198,383
→
METHOD FOR PRODUCING A DIELECTRIC INTERLAYER AND STORAGE CAPACITOR WITH SUCH A DIELECTRIC INTERLAYER
App. No. 12/198,005
→
ELECTRONIC DEVICE HAVING A CHIP STACK
App. No. 12/196,215
→
INTEGRATED CIRCUIT INCLUDING MEMORY CELL HAVING CUP-SHAPED ELECTRODE INTERFACE
App. No. 12/195,964
→
INTEGRATED CIRCUIT AND PROGRAMMABLE DELAY
App. No. 12/195,120
→
HIGH SPEED MEMORY ARCHITECTURE
App. No. 12/194,414
→
METHOD AND APPARATUS FOR FAST AND LOCAL ANNEAL OF ANTI-FERROMAGNETIC (AF) EXCHANGE-BIASED MAGNETIC STACKS
App. No. 12/193,786
→
INTEGRATED CIRCUIT WITH BIT LINES POSITIONED IN DIFFERENT PLANES
App. No. 12/193,267
→
CIRCUIT WITH SELECTABLE DATA PATHS
App. No. 12/193,698
→
METHOD FOR FABRICATING A NANOELEMENT FIELD EFFECT TRANSISTOR WITH SURROUNDED GATE STRUCTURE
App. No. 12/190,379
→
ARRAY OF LOW RESISTIVE VERTICAL DIODES AND METHOD OF PRODUCTION
App. No. 12/188,401
→
INTEGRATED CIRCUIT INCLUDING SELECTABLE ADDRESS AND DATA MULTIPLEXING MODE
App. No. 12/188,558
→
INTEGRATED CIRCUIT COMPRISING AN ORGANIC SEMICONDUCTOR, AND METHOD FOR THE PRODUCTION OF AN INTEGRATED CIRCUIT
App. No. 12/188,966
→
METHOD OF OPERATING A MEMORY APPARATUS, MEMORY DEVICE AND MEMORY APPARATUS
App. No. 12/186,195
→
SEMICONDUCTOR MEMORY AND METHOD FOR OPERATING A SEMICONDUCTOR MEMORY
App. No. 12/186,085
→
BUS TERMINATION SYSTEM AND METHOD
App. No. 12/185,472
→
ALIGNMENT CALCULATION
App. No. 12/184,798
→
FIELD EFFECT TRANSISTORS WITH CHANNELS ORIENTED TO DIFFERENT CRYSTAL PLANES
App. No. 12/182,419
→
INTEGRATED CIRCUIT INCLUDING AN ARRAY OF MEMORY CELLS AND METHOD
App. No. 12/182,698
→
INTEGRATED CIRCUIT AND METHOD OF FORMING AN INTEGRATED CIRCUIT
App. No. 12/182,714
→