Integrated circuit with stacked devices
View Patent ↗An integrated circuit with stacked devices. One embodiment provides a surface of a first semiconductor structure of a first crystalline semiconductor material including first and second portions. First structures are formed on the first portions. The second portions remain uncovered. Sacrificial structures of a second, different crystalline material are formed on the second portions. A second semiconductor structure of the first crystalline semiconductor material is formed over the sacrificial structures and over the first structures.
1. A method of manufacturing an integrated circuit, the method comprising:
forming first structures on first portions of a surface of a first semiconductor structure of a first crystalline semiconductor material;
forming sacrificial structures of a second crystalline material on second portions of the surface between the first portions, wherein the first crystalline semiconductor material is effective as a crystal seed for the second crystalline material;
forming a second, crystalline semiconductor structure of the first crystalline semiconductor material over the sacrificial structures and over the first structures, wherein the sacrificial structures are effective as a crystal seed for the first crystalline semiconductor material; and
removing the sacrificial structures to form voids between neighboring first structures respectively.
2. The method of claim 1 , wherein the second crystalline material is a second crystalline semiconductor material different from the first crystalline semiconductor material.
3. The method of claim 1 , wherein a first lattice constant of the first crystalline semiconductor material and a second lattice constant of the second crystalline material deviate by at most 10% from each other.
4. The method of claim 1 , wherein the first crystalline semiconductor material is single-crystalline silicon.
5. The method of claim 4 , wherein the second crystalline material has a cubic diamond lattice structure.
6. The method of claim 4 , wherein the second crystalline material is a silicon germanium alloy.
7. The method of claim 4 , wherein the first semiconductor structure is a silicon wafer or a silicon layer arranged upon a dielectric base.
8. The method of claim 1 , further comprising:
forming second structures on the second semiconductor structure.
9. The method of claim 1 , further comprising:
forming source/drain regions and channel regions of field effect transistor structures in the second semiconductor structure, wherein the channel regions are formed in a vertical projection above the sacrificial structures.
10. The method of claim 1 , further comprising:
forming source/drain regions and channel regions of field effect transistor structures in the second semiconductor structure, wherein the source/drain regions are formed in a vertical projection above the sacrificial structures.
11. The method of claim 1 , further comprising:
removing first portions of the second semiconductor structure at least partly to uncover portions of the sacrificial structures, before removing the sacrificial structures.
12. The method of claim 1 , wherein the first structures are gate electrodes of memory cells arranged to NAND strings.
13. A method of manufacturing an integrated circuit, comprising:
forming first gate structures arranged along a string on first portions of a surface of a first semiconductor structure of a first crystalline semiconductor material;
forming sacrificial structures of a second crystalline material on second portions of the surface between the first portions;
forming a second semiconductor structure of the first crystalline semiconductor material on the sacrificial structures and above the first gate structures, wherein the first portions are effective as a crystal seed for the sacrificial structures and the sacrificial structures are effective as a crystal seed for the second semiconductor structure;
removing first portions of the second semiconductor structure to uncover portions of the sacrificial structures; and
removing the sacrificial structures at least partly to form voids between neighboring first gate structures respectively.
14. The method of claim 13 , wherein the first crystalline semiconductor material is single-crystalline silicon.
15. The method of claim 14 , wherein the second crystalline material is a silicon germanium alloy.
16. The method of claim 13 , further comprising:
forming second gate structures arranged to strings on the second semiconductor structure.
17. The method of claim 16 , comprising forming the second gate structures in a vertical projection of the sacrificial structures.
18. A method of manufacturing an integrated circuit, the method comprising:
covering first portions of a surface of a first semiconductor carrier with a cover material, the first semiconductor carrier comprising a first crystalline semiconductor material;
forming a sacrificial crystalline material over second portions of the surface between the first portions, wherein the first crystalline semiconductor material is effective as a crystal seed;
forming first crystalline semiconductor material over the sacrificial crystalline material and over the first portions, wherein the sacrificial crystalline material is effective as a crystal seed; and
removing the sacrificial crystalline material at least partly to form voids between neighboring first portions respectively.