Patent Assignment
Reel/Frame 051917/0581
Assignment of Assignor's Interest
Recorded: 2020-02-12
Pages: 9
Assignor
POLARIS INNOVATIONS LIMITED
Executed: 2019-11-30
Assignee
CHANGXIN MEMORY TECHNOLOGIES, INC
ROOM 630, HAIHENG BUILDING, NO. 6, CUIWEI ROAD, ECONOMIC AND TECHNOLOGICAL DEVELOPMENT ZONE, HEFEI, ANHUI, 230000, CHINA
Covered Properties
(83)
Semiconductor Device Fabrication Using a Photomask Designed Using Modeling and Empirical Testing
Patent:
6,571,383 →
Application:
09/562,700 →
Method for Fabricating a Microtechnical Structure
Patent:
6,413,886 →
Application:
09/636,522 →
Patterning of Contact Areas in Multilayer Metalization Configurations of Semiconductor Components
Patent:
6,559,547 →
Application:
09/663,569 →
Integrated Circuit Having a Self-Test Device for Carrying Out a Self-Test of the Integrated Circuit
Fuse Configuration for a Semiconductor Apparatus
Dry Polymer and Oxide Veil Removal for Post Etch Cleaning
Patent:
6,479,396 →
Application:
09/794,055 →
Metal Hard Mask for Ild Rie Processing of Semiconductor Memory Devices to Prevent Oxidation of Conductive Lines
Integrated Semiconductor Circuit, in Particular a Semiconductor Memory Configuration, and Method for Its Operation
Field-Effect Transistor Structure with an Insulated Gate
Fuse Circuit Configuration
Semiconductor Configuration Having an Optical Fuse
Method for Fabricating a Barrier Layer
Integrated Circuit with Test Mode, and Test Configuration for Testing an Integrated Circuit
Connection Element
Circuit Configuration for Switching Over a Receiver Circuit in Particular in Dram Memories and Dram Memory Having the Circuit Configuration
Chip Id Register Configuration
Method for High Aspect Ratio Gap Fill Using Sequential Hdp-Cvd
Method and Device for Producing a Metal/Metal Contact in a Multilayer Metallization of an Integrated Circuit
Method for Producing an Electrically Conducting Connection
Method of Forming a Self-Aligned Antifuse Link
Patent:
6,465,282 →
Application:
09/966,332 →
Configuration for Fuse Initialization
System and Method for Storing Parity Information in Fuses
Self-Terminating Blow Process of Electrical Anti-Fuses
Process for Implementation of a Hardmask
Patent:
6,541,387 →
Application:
10/052,201 →
Method and Circuit Configuration for Identifying an Operating Property of an Integrated Circuit
Circuit for Synchronizing Signals During the Exchange of Information Between Circuits
Method for Testing Semiconductor Chips
Process for Depositing Wsix Layers on a High Topography with a Defined Stoichiometry
Method for Testing Circuit Units to Be Tested with Increased Data Compression for Burn-In
Electronic Circuit for Generating an Output Voltage Having a Defined Temperature Dependence
Wafer with Additional Circuit Parts in the Kerf Area for Testing Integrated Circuits on the Wafer
System and Method for Enabling a Vendor Mode on an Integrated Circuit
Method and Circuit for Controlling Fuse Blow
Reflection Mask for Euv-Lithography and Method for Fabricating the Reflection Mask
High Density Dram with Reduced Peripheral Device Area and Method of Manufacture
Method for Forming a Hard Mask in a Layer on a Planar Device
Method for Filling Depressions on a Semiconductor Wafer
Semiconductor Configuration and Process for Etching a Layer of the Semiconductor Configuration Using a Silicon-Containing Etching Mask
Production Method for a Semiconductor Component
Method for the Formation of Contact Holes for a Number of Contact Regions for Components Integrated in a Substrate
Photolithographic Patterning Process Using a Carbon Hard Mask Layer of Diamond-Like Hardness Produced by a Plasma-Enhanced Deposition Process
Method for Contacting Parts of a Component Integrated into a Semiconductor Substrate
Circuit Configuration for Driving a Programmable Link
Circuit Configuration for Reading Out a Programmable Link
Method for Etching a Hard Mask Layer and a Metal Layer
Semiconductor Device Testing Apparatus, Semiconductor Device Testing System, and Semiconductor Device Testing Method for Measuring and Trimming the Output Impedance of Driver Devices
Method for Forming a Structure Element on a Wafer by Means of a Mask and a Trimming Mask Assigned Hereto
Temperature Sensor Scheme
Input Receiver Circuit
Input Return Path Based on Vddq/Vssq
Integrated Semiconductor Circuit with an Electrically Programmable Switching Element
System and Method for Enabling a Vendor Mode on an Integrated Circuit
Semiconductor Device with Test Circuit Disconnected from Power Supply Connection
Integrated Memory and Method for Functional Testing of the Integrated Memory
Input Switching Arrangement for a Semiconductor Circuit and Test Method for Unidirectional Input Drivers in Semiconductor Circuits
Memory Having Test Circuit
High Dielectric Constant Materials
Method for Fabricating a Dram Memory Cell Arrangement Having Fin Field Effect Transistors and Dram Memory Cell
Method and Apparatus for Selectively Accessing and Configuring Individual Chips of a Semi-Conductor Wafer
Method of Producing a Structure on the Surface of a Substrate
Method of Producing Pitch Fractionizations in Semiconductor Technology
Fuse Resistance Read-Out Circuit
Method for Testing an Integrated Semiconductor Memory
Random Access Memory Including Circuit to Compress Comparison Results
Driver Circuit for Binary Signals
Method for Fabricating an Integrated Circuit on a Semiconductor Substrate
Memory Device and Method for Testing Memory Devices with Repairable Redundancy
Parallel Read for Front End Compression Mode
Finding a Data Pattern in a Memory
Memory Including a Write Training Block
Standby Current Reduction Over a Process Window with a Trimmable Well Bias
Manufacturing Method for an Integrated Semiconductor Structure
Semiconductor Devices and Methods of Manufacture Thereof
Integrated Semiconductor Memory with Generation of Data
Integrated Circuit Device Having Openings in a Layered Structure
Method for Self-Test and Self-Repair in a Multi-Chip Package Environment
Controlling an Analog Signal in an Integrated Circuit
Method for Producing a Structure on the Surface of a Substrate
Integrated Circuits Having a Contact Structure Having an Elongate Structure and Methods for Manufacturing the Same
Digital Data Inversion Flag Generator Circuit
Integrated Circuit with Control Circuit for Performing Retention Test
Integrated Circuit with Stacked Devices
Integrated Circuit Comprising Conductive Lines and Contact Structures and Method of Manufacturing an Integrated Circuit
Related Assignments
(13)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jan 13, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023828/0001 →
Assignment of Assignor's Interest
Jan 13, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023773/0001 →
Assignment of Assignor's Interest
Jan 13, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023773/0457 →
Assignment of Assignor's Interest
Jan 13, 2010
From: INFINEON TECHNOLOGIES NORTH AMERICA CORP
To: QIMONDA AG
Reel/Frame 023774/0399 →
Assignment of Assignor's Interest
Jan 13, 2010
From: INFINEON TECHNOLOGIES RICHMOND, LP
To: QIMONDA AG
Reel/Frame 023792/0001 →
Assignment of Assignor's Interest
Jan 15, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023853/0001 →
Assignment of Assignor's Interest
May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
Assignment of Assignor's Interest
Aug 7, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036305/0890 →
Assignment of Assignor's Interest
Aug 19, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036396/0646 →
Assignment of Assignor's Interest
Sep 3, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036539/0196 →
Assignment of Assignor's Interest
Sep 9, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036575/0368 →
Assignment of Assignor's Interest
Oct 7, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036808/0284 →
Assignment of Assignor's Interest
Oct 19, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036888/0745 →