Patent Assignment
Reel/Frame 023773/0001
Assignment of Assignor's Interest
Recorded: 2010-01-13
Received: 2010-01-13
Pages: 398
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2006-04-25
Assignee
QIMONDA AG
GUSTAV-HEINEMANN-RING 212, MUNICH, DEX, 81739, GERMANY
Covered Properties
(100)
Memory Circuit, a Dynamic Random Access Memory, a System Comprising a Memory and a Floating Point Unit and a Method for Storing Digital Data
Application:
11/530,858 →
Method and Apparatus for Sending Data from a Memory
Application:
11/530,015 →
Method and Device for Verifying Output Signals of an Integrated Circuit
Application:
11/469,365 →
Memory Element Comprising Non-Graphitic Disorered Carbon and Using Reversible Switiching Between SP2 and SP3 Hybirdization States
Application:
11/510,512 →
Programmable non-volatile memory cell
Application:
11/497,528 →
Method of Forming a Doped Portion of a Semiconductor and Method of Forming a Transistor
Application:
11/493,028 →
Method and Memory Circuit for Operating a Resistive Memory Cell
Application:
11/459,289 →
Apparatus and Method for Controlling a Driver Strength
Application:
11/457,133 →
Buried Bitline with Reduced Resistance
Application:
11/478,313 →
Memory Element, Memory Read-Out Element and Memory Cell
Application:
11/427,337 →
Multi-Context Memory Cell
Application:
11/427,336 →
Die Configurations and Methods of Manufacture
Application:
11/475,720 →
Memory Device, in Particular Phase Change Random Access Memory Device with Transistor, and Method for Fabricating a Memory Device
Application:
11/445,801 →
Electronic Memory Apparatus and Method for Operating an Electronic Memory Apparatus
Application:
11/444,914 →
Memory Cell Array and Method of Forming a Memory Cell Array
Application:
11/443,432 →
Circuit board arrangement
Application:
11/443,494 →
Contact Structure for a Stack Dram Storage Capacitor
Application:
11/439,441 →
Semiconductor Memory Module
Application:
11/439,443 →
Method for Producing a Dielectric Interlayer and Storage Capacitor with Such a Dielectric Interlayer
Application:
11/438,700 →
Semiconductor Memory Component
Application:
11/438,883 →
Delay Locked Loop and Method for Setting a Delay Chain
Application:
11/437,825 →
Memory Module with an Electronic Printed Circuit Board and a Plurality of Semiconductor Chips of the Same Type
Application:
11/437,846 →
Controllable Delay Device
Application:
11/382,231 →
Vertical Device with Sidewall Spacer, Methods of Forming Sidewall Spacers and Field Effect Transistors, and Patterning Method
Application:
11/414,553 →
Method for Fabricating a Semiconductor Component and Semiconductor Component
Application:
11/413,320 →
Circuit and a Method of Determining the Resistive State of a Resistive Memory Cell
Application:
11/406,803 →
Method for Fabricating an Electrical Component
Application:
11/399,811 →
Method for Fabricating a Nonvolatile Memory Element and a Nonvolatile Memory Element
Application:
11/398,852 →
Method and System for the Optical Inspection of Contact Faces at Semiconductor Devices with Different Appearances
Application:
11/399,228 →
Methods of Ddr Receiver Read Re-Synchronization
Application:
11/397,429 →
Semiconductor Having Structure with Openings
Application:
11/395,111 →
Method for Patterning a Semiconductor Component
Application:
11/392,523 →
Method for Initialization of Electronic Circuit Units, and Electric Circuit
Application:
11/392,522 →
Charge Trapping Device and Method of Producing the Charge Trapping Device
Application:
11/390,997 →
Method for Forming an Integrated Memory Device and Memory Device
Application:
11/390,983 →
Reducing Leakage Current in Memory Device Using Bitline Isolation
Application:
11/387,879 →
Manufacturing Method for an Integrated Semiconductor Structure
Application:
11/388,234 →
Finding a Data Pattern in a Memory
Application:
11/386,176 →
Memory Including an Output Pointer Circuit
Application:
11/386,510 →
Filtering Bit Position in a Memory
Application:
11/386,377 →
Memory Including a Write Training Block
Application:
11/386,360 →
Memory with a Temperature Sensor, Dynamic Memory and Memory with a Clock Unit and Method of Sensing a Temperature of a Memory
Application:
11/386,048 →
Parallel Read for Front End Compression Mode
Application:
11/385,340 →
Intergrated Circuit Including Resistivity Changing Material Element
Application:
11/378,201 →
Method of Forming Self-Aligned Air-Gaps Using Self-Aligned Capping Layer over Interconnect Lines
Application:
11/276,801 →
Method of Forming a Contact to Memory Cell Pillar Electrode by Surrounding Pillar with Mutiple Dielectric Layers Having Different Polishing Characteristics
Application:
11/376,445 →
Hard Mask Layer Stack and a Method of Patterning
Application:
11/376,645 →
Integrated Circuit Having A Memory Cell
Application:
11/375,365 →
Memory Circuit, Method for Operating a Memory Circuit, Memory Device and Method for Producing a Memory Device
Application:
11/374,413 →
Method for Determining an Edge Profile of a Volume of a Photoresist After a Development Process
Application:
11/371,237 →
Integrated Semiconductor Memory Device
Application:
11/370,172 →
Memory Device and Method for Operating Such a Memory Device
Application:
11/369,275 →
Methods for Generating a Reference Voltage and for Reading a Memory Cell and Circuit Configurations Implementing the Methods
Application:
11/368,266 →
Phase Change Memory Fabricated Using Self-Aligned Processing
Application:
11/366,706 →
Phase Change Memory Fabricated Using Self-Aligned Processing
Application:
11/366,370 →
Phase Change Memory Fabricated Using Self-Aligned Processing
Application:
11/366,151 →
Semiconductor Memory Module and Electronic Apparatus Including a Semiconductor Memory Module and Method for Operating Thereof
Application:
11/364,135 →
Method and Apparatus for Calibration of an on-Chip Temperature Sensor Within a Memory Device
Application:
11/354,955 →
Method and Apparatus for an Oscillator Within a Memory Device
Application:
11/354,985 →
Method of Fabricating a Contact for a Semiconductor Device
Application:
11/352,446 →
Memory having nanotube transistor access device
Application:
11/350,191 →
Shared Interface for Components in an Embedded System
Application:
11/349,631 →
Intergrated Circuit Having Resistive Memory Cells
Application:
11/348,640 →
Semiconductor Memory Module with Bus Architecture
Application:
11/346,570 →
Data Handover Unit for Transferring Data Between Different Clock Domains by Parallelly Reading Out Data Bits from a Plurality of Storage Elements
Application:
11/346,993 →
Clock and Data Recovery Circuit Having Gain Control
Application:
11/346,905 →
Circuit Board for Reducing Crosstalk of Signals
Application:
11/345,626 →
Transistor, memory cell and method of manufacturing a transistor
Application:
11/343,812 →
Integrated circuit arrangement
Application:
11/344,960 →
Method of transmitting data between different clock domains
Application:
11/343,946 →
Semiconductor wafer having measurement area feature for determining dielectric layer thickness
Application:
11/343,052 →
Stack of Semiconductor Chips
Application:
11/341,884 →
Storage Capacitor for Semiconductor Memory Cells and Method of Manufacturing a Storage Capacitor
Application:
11/339,744 →
System Method for Performing a Direct Memory Access for Automatically Copying Initialization Boot Code in a New Memory Architecture
Application:
11/337,754 →
Test Parallelism Increase by Tester Controllable Switching of Chip Select Groups
Application:
11/333,037 →
Memory Data Bus Structure and Method of Transferring Information with Plural Memory Banks
Application:
11/327,354 →
Memory Device and a Method of Forming a Memory Device
Application:
11/327,054 →
Integrated Circuit Memory Having a Read Circuit
Application:
11/326,235 →
Test Mode for Ipp Current Measurement for Wordline Defect Detection
Application:
11/322,252 →
Integrated Circuit Having a Resistive Memory
Application:
11/324,700 →
Method of Manufacturing a Field Effect Transistor Device with Recessed Channel and Corner Gate Device
Application:
11/321,450 →
Method of Fabricating an Integrated Circuit
Application:
11/320,489 →
Method for Fabricating an Integrated Circuit on a Semiconductor Substrate
Application:
11/319,793 →
Edge Pad Architecture for Semiconductor Memory
Application:
11/320,266 →
Resistive Memory Device and Method for Writing to a Resistive Memory Cell in a Resistive Memory Device
Application:
11/318,331 →
Memory Circuit Including a Resistive Memory Element and Method for Operating Such a Memory Circuit
Application:
11/318,345 →
Write Burst Stop Function in Low Power Ddr Sdram
Application:
11/314,529 →
Random Access Memory Including Circuit to Compress Comparison Results
Application:
11/314,605 →
Memory Cell Arrays and Methods for Producing Memory Cell Arrays
Application:
11/313,247 →
Circuit Board Arrangement Including Heat Dissipater
Application:
11/311,701 →
Methods for Elimination or Reduction of Oxide and/or Soot Deposition in Carbon Containing Layers
Application:
11/303,639 →
Semiconductor Memory Device with Channel Regions Along Sidewalls of Fins
Application:
11/304,062 →
Transistor, Memory Cell, Memory Cell Array and Method of Forming a Memory Cell Array
Application:
11/300,853 →
Embedded Testing Circuit for Testing a Dual Port Memory
Application:
11/291,099 →
Method of Modeling Physical Layout of an Electronic Component in Channel Simulation
Application:
11/272,023 →
Apparatus for Processing a Substrate
Application:
11/273,244 →
Memory Device That Provides Test Results to Multiple Output Pads
Application:
11/273,058 →
Method and Apparatus for Reducing Standby Current in a Dynamic Random Access Memory During Self Refresh
Application:
11/270,178 →
Memory Device with a Plurality of Memory Cells, in Particular Pcm Memory Cells, and Method for Operating Such a Memory Cell Device
Application:
11/269,898 →
Phase Change Memory Having Multilayer Thermal Insulation
Application:
11/265,372 →