IP Library Granted Patent US 7,416,952
Granted Patent B2
US 7,416,952 · App. 11/438,700 · Granted Aug 26, 2008

Method for producing a dielectric interlayer and storage capacitor with such a dielectric interlayer

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Quick Facts
Patent No.
US 7,416,952
App. No.
11/438,700
Granted
Aug 26, 2008
Kind
B2
Abstract

A dielectric interlayer, especially for a storage capacitor, is formed from a layer sequence subjected to a temperature process, wherein the layer sequence has at least a first metal oxide layer and a second metal oxide layer formed by completely oxidizing a metal nitride layer to higher valency.

Claims (24)

1. A method for producing a dielectric interlayer for use in a storage capacitor of a semiconductor memory cell, comprising:

forming a first metal oxide layer;

forming a metal nitride layer;

oxidizing the metal nitride layer to higher valency to form a second metal oxide layer; and

heating the layer sequence to form a mixed layer from the first and the second metal oxide layer.

2. The method according to claim 1 , wherein

the first metal oxide is any of alumina, titanium oxide, tantalum oxide, hafnium oxide, zirconium oxide and an oxide of the lanthanum group, and

the metal nitride is any of aluminum nitride, titanium nitride, tantalum nitride, hafnium nitride, zirconium nitride, silicon nitride and a nitride of the lanthanum group.

3. The method according to claim 2 , wherein the first metal oxide is alumina and the metal nitride is titanium nitride.

4. The method according to any claim 1 , wherein the layers are formed with an atomic layer deposition.

5. The method according to claim 4 , wherein a further first metal oxide layer is applied onto the second metal oxide layer, wherein oxidizing the metal nitride layer to higher valency to form the second metal oxide layer is effected by the aid of the oxygen precursor of the first metal oxide layer.

6. A method for producing a storage capacitor for use in a semiconductor storage cell, comprising:

forming a first electrode layer;

forming a dielectric interlayer on the first electrode layer; and

forming a second electrode layer on the dielectric interlayer;

wherein the dielectric interlayer is formed including:

forming a first metal oxide layer;

forming a metal nitride layer;

oxidizing the metal nitride layer to higher valency to form a second metal oxide layer; and

heating the layer sequence to form a mixed layer from the first and the second metal oxide layer.

7. The method according to claim 6 , wherein a trench is realized in a semiconductor substrate,

the first electrode layer is formed in the semiconductor substrate around the trench,

the dielectric interlayer is realized on the trench wall, and

the second electrode layer is formed on the dielectric interlayer.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 30, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 037171/0719 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 19, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 037147/0487 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023773/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2006
From: HINTZE, BERND; BERNHARDT, HENRY; BENRNHARDT, FRANK
To: INFINEON TECHNOLOGIES AG
Reel/Frame 018182/0480 →